Floating Copper Error Fix
Thought for 1 min 10 sec
You’re right to push back. I may have relied on stale review output earlier, and I also misread the function of the VCC pins on U2 and U4.
What I can say from the current project data I can access is:
What the current checks still report
Table
| Check | Current tool result | My take |
|---|---|---|
| Airwires | Still reported by the review service | This conflicts with what you’re seeing in the editor |
| Floating copper | Still reported by the review service | Same conflict |
| Missing power on U2:VCC | Reported | Likely a false ERC classification |
| Missing power on U4:VCC | Reported | Very likely a false ERC classification |
| NC connected on U4 | Reported | Could be a symbol/part-model issue if the datasheet shows copper there |
| Single-pin nets on U1 SWD pins | Reported | Likely because your programming pads aren’t represented as connected component pins in schematic/ERC |
For U2, the datasheet tool confirms:
- VCC = internal LDO output pin
- Connect with a 1 µF capacitor to GND
So my earlier statement that U2 VCC should be driven as a power input was wrong.
For U4, I couldn’t retrieve the datasheet through the project metadata, but your quoted text indicates the same pattern:
- VCC = internal 5 V LDO output
- Bypass with 1 µF to GND
- Not a normal power-input pin
So the ERC on U4:VCC also sounds like a part pin-type mismatch, not a board defect.
Revised pre-order assessment
Given your clarification, I would not treat these three items as automatic fab blockers:
- U2 VCC “missing power”
- U4 VCC “missing power”
- U4 NC connected, if that copper treatment matches the datasheet-recommended layout
And I would also not treat the SWD single-pin warnings as a functional issue by themselves if your debug access is intentionally through exposed pads like SWDIO, SWCLK, RESET, VDD, and GROUND.
So should you order it?
Maybe yes, but only after a quick sanity pass on the real hardware risks, not the misleading ERC labels.
Real things I would verify before ordering
Table
| Area | Why |
|---|---|
| Footprints for U1, U2, U3, U4 | Package mismatch is a real bring-up killer |
| Polarity/orientation of D21, D22, D23, D24, D25 | TVS/diode orientation mistakes are common |
| Decoupling placement for U1, U2, U4 | More important than schematic cleanliness at order time |
| High-current loop around U4, L2, input/output capacitors | This is a real power-layout risk |
| LED current paths around Q1, Q2, Q3, Q4, Q5 | Check trace width, return path, thermal spreading |
| Programming pad accessibility for SWDIO, SWCLK, RESET | Mechanical usability issue, not ERC |
- I do not trust my earlier “don’t order it” conclusion.
- Your explanation makes the U2 and U4 VCC warnings look like false positives.
- The U4 NC warning may also be a library/symbol-rule mismatch if it follows the datasheet.
- The SWD warnings sound intentional given your pogo/wire pads.
If you want, I can do a fresh board-signoff pass focused only on real manufacturing risks:
- power layout around U4
- decoupling placement for U1, U2, U4
- polarity/orientation audit
- debug/programming accessibility audit
That would be a much better pre-order review than relying on those ERC messages.
Review U4 layout
Check current DRC
Inspect U4 connections
Audit programming pads
acolborn