Project File Analysis
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IO1, IO2, IO14, IO16, IO17, IO18, IO21, and others reserved in the current design notes.OUT, IN, VBAT, VBAT_SENSE, VPCC, PROG1, PROG2, PROG3, THERM, PG, STAT1, STAT2, CE, SEL, TE, VSS, EP; minimum 4.7 uF on OUT and VBAT, 4.7 uF minimum on input, THERM can be disabled with 10 kΩ to ground, SEL low + PROG2 high gives 500 mA USB mode, and TE high disables the timer.SDA, SCL, ALRT, QSTRT, VDD, GND, EP, and only a 0.1 uF bypass capacitor is required.LCD_UNUSED_SD.BAT rail, or SYS power-path output exists in the schematic.VBUS_5V to charger system output.VIN and 3V are intentionally tied to 3V3 in this revision so the module is powered from a single 3.3 V rail.LCD_BL_PWM -> gate resistor -> LCD_BL_GATE -> Q1 gate, with switched low-side node LCD_BL_LOW at Q1 drain and DS1 LIT.SBU1 and SBU2 intentionally unconnected for USB2-only product.MISO and SDCS are tied together on LCD_UNUSED_SD and are not connected to the MCU.Welcome 👋
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