Schematic Reconstruction Gap Review
Scope reviewed
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The available material communicates the architecture and many component values, but it is not yet a fabrication-grade schematic/netlist. The SVGs are conceptual drawings rather than EDA exports and omit critical pins, part identities, and exact connectivity.
Blocking information needed before an electrically faithful reconstruction
1. Exact filter parts and pinouts
The following parts are specified only by frequency range:
- F1: 400–510 MHz SAW
- F2: 698–960 MHz LTCC
- F3: 2.4–2.5 GHz SAW
Required for each: manufacturer, MPN, package/land pattern, input/output pin numbers, ground pins, whether the device is internally matched to 50 Ω, and any required external matching network. “国产替代 / SMD” is insufficient to choose a symbol, footprint, or connectivity.
2. RF front-end topology and impedance definition
The antenna is shown connected to six filters through a direct parallel bus described as “粗能量分配不做匹配.” A reconstructable schematic still needs:
- exact six-way branch topology and named RF nets;
- whether isolation/series resistors, coupling capacitors, or matching components are fitted or DNP;
- source/load impedance assumptions for every channel;
- exact “匹配杂项被动组” parts, values, designators, and placement by channel;
- PCB antenna feed structure, ground reference, matching/tuning footprint, and intended antenna geometry.
The claimed single PCB antenna coverage of 0.7–6 GHz also needs a defined, simulated or measured geometry; the PCB image is only illustrative.
3. CH6 microstrip filter implementation
The document gives only a target band and approximate 50 Ω trace width. Reconstruction needs the complete filter geometry: topology, resonator widths/lengths, gaps, tap positions, feed transitions, copper layer, ground/via-fence arrangement, solder-mask treatment, and stackup dielectric data. The illustrative SVG polyline cannot define a 5.8 GHz filter.
4. Detector polarity and RF connection details
For D1–D6 (SMS7630-040LF), confirm:
- diode anode/cathode orientation;
- exact SOD-882 footprint and pin mapping;
- whether the filter output connects directly to the diode or through a DC-block/matching network;
- RF return/ground implementation;
- whether 100 pF is valid on all six channels or channel-specific values are intended.
5. Complete op-amp connectivity
The drawing identifies U1A–U1D and U2A–U2B, but omits package pin numbers and explicit power wiring. Required:
- verified SGM8044 orderable MPN/package and pinout;
- mapping of each channel to physical amplifier pins;
- U1/U2 V+ and V− connections;
- exact C61/C62 connection and whether bulk decoupling is also required;
- disposition of unused U2C/U2D with physical pin mapping;
- confirmation that the op-amp input common-mode range, output swing, LED load drive, and stability are acceptable over VRAIL = 1.8–5.1 V.
The present gain network is conceptually clear: 30 kΩ feedback and 1 kΩ to ground, gain ≈31.
6. LED circuit definition
Required:
- LED MPN or minimum electrical/optical specification;
- polarity/orientation;
- confirmation that each LED and 680 Ω resistor are connected from op-amp output to ground as drawn;
- desired color consistency and threshold tolerance over supply voltage;
- whether all six outputs may illuminate simultaneously and the resulting current budget.
7. Exact XIAO variant and connector pin mapping
The files alternately allow “ESP32-S3 / SAMD21.” These have different capabilities and pin mappings. Choose one primary module and provide:
- exact XIAO product/MPN and footprint/header strategy;
- physical pad-to-signal mapping for A0–A5, 5V, GND, SDA, SCL, and wake/GPO;
- whether the module is soldered castellated, socketed, or DNP;
- confirmation that every selected analog pin tolerates the possible op-amp output voltage;
- boot-state/back-powering requirements.
8. ST25DV device variant, package, and full support circuit
“ST25DV16K, SO-8” is not enough and may not match the selected device’s actual pin/package variant. Required:
- full orderable MPN;
- verified package and pinout;
- RF coil pin connections;
- I²C address/configuration pins and their pull-up values/rail;
- SDA/SCL/GPO physical connections to the chosen XIAO;
- EH and VCC power-pin treatment;
- required decoupling;
- GPO pull-up and polarity;
- NFC coil tuning/matching capacitors and target resonant frequency.
The current BOM and schematic do not include the NFC tuning network, I²C pull-ups, or clear ST25DV supply-domain wiring.
9. NFC coil electrical design
The PCB reference says 15 × 24 mm, while the BOM says approximately 25 × 35 mm. Resolve this conflict and provide: turn count, trace width/spacing, copper thickness/layer, inductance target, resistance/Q target, tuning capacitance, keepout, and connection polarity. The image is not dimensionally sufficient for a working 13.56 MHz harvester.
10. Power ORing netlist and diode orientation
The conceptual power drawing needs an explicit pin-level netlist. Clarify:
- named nodes for ST25DV EH output, supercapacitor node, CR2032 node, XIAO 5 V, and VRAIL;
- intended purpose of both D10 and D11 in series on the NFC path;
- exact anode/cathode orientation of D10–D13 and ZD1;
- whether D12 or D13 naming agrees with the BOM note (“档1仅D12”) and project text;
- supercapacitor polarity, footprint, leakage requirement, and whether inrush/current limiting is needed;
- CR2032 holder MPN, polarity, and whether the battery is actually fitted in Tier 1;
- VRAIL discharge path and behavior when sources are absent or hot-plugged.
11. Missing CH1 LNA/load-switch circuitry
The notes mention a DNP PSA4-5043+ LNA and a Si2302 load switch for CH1, but neither is fully represented in the BOM or schematic. Decide whether these footprints are part of v0.5. If retained, provide the complete LNA bias, RF matching/DC blocking, MOSFET gate control, pull resistors, supply decoupling, designators, and DNP rules. If deleted, remove the references from the specification.
12. Complete designator-level BOM
The BOM groups multiple components into aggregate rows, so it cannot generate the schematic directly. A reconstruction BOM must list every physical part separately, including:
- C1–C5, L1–L5;
- C11–C16, R11–R16, R21–R26, R31–R36, R41–R46, R51–R56;
- C61/C62 and all missing power/NFC support passives;
- D1–D6, D10–D13, ZD1, LED1–LED6;
- F1–F3, U1–U3, BT1, XIAO/module headers, and any DNP footprints.
For each: value, tolerance, voltage/current rating, dielectric/material where relevant, MPN, package, footprint, population tier, and approved alternatives.
Important conflicts and ambiguities
- Tier BOM attachment is inaccessible (HTTP 403).
- NFC coil size: 25 × 35 mm in BOM versus 15 × 24 mm in the project/PCB drawing.
- PCB cost note references an obsolete 120 × 50 estimate, while the current outline is 120 × 30 mm.
- Tier 1 BOM includes a CR2032 holder and battery, while the tier description says “无 MCU 无电池，tap 即亮.”
- Tier 1 BOM says only D12 is fitted, but the NFC harvesting path in the drawing uses D10 and D11; this is electrically inconsistent.
- XIAO variant is undecided (ESP32-S3 versus SAMD21).
- ST25DV exact variant/package is unspecified.
- The main text mentions four ORing diodes D10–D13, but the functional role and tier population of each is not consistently documented.
- “2 vias only” is a conceptual placement claim, not a routable constraint for all six detector outputs, power, ground, I²C, and RF structures.
Non-blocking but strongly recommended information
- Named net list and intended net labels.
- Test points for VRAIL, each detector output, NFC EH, supercap, and ground.
- ERC intent: intentionally paralleled sources, unused pins, and DNP connections.
- Maximum current/power budget for each source and simultaneous LED operation.
- Grounding/partition strategy between RF, detector, LED return, NFC coil, and digital module.
- ESD protection requirements for exposed/user-accessible points.
- Environmental and manufacturing constraints, including component height and assembly side limits.
- Calibration procedure and expected detector transfer curve/channel thresholds.
Minimum input package to proceed
- Re-upload the tier BOM or provide it as CSV/XLSX with accessible permissions.
- Supply exact MPNs/datasheets for F1, F2, F3, U3, the XIAO variant, CR2032 holder, supercapacitor, and LEDs.
- Provide a designator-level BOM rather than grouped “component sets.”
- Confirm the explicit source-to-VRAIL power netlist and diode orientations.
- Provide the ST25DV coil/tuning circuit and final coil dimensions.
- Provide the CH6 microstrip filter dimensions or an EM/PCB source file.
- Decide whether the CH1 LNA/load switch is included or removed.
- Confirm Route A Tier 1 or Tier 2 as the first reconstruction target.
Once those items are resolved, the schematic can be reconstructed with verified symbols, footprints, pin mappings, population variants, and a deterministic netlist.