PCB Design Help

flux

Updated the Designator-Level BOM with both preliminary selections. F2 remains explicitly provisional pending validation of its unused high-band port; F3 includes its verified pinout and no-match requirement.
256ericpan

256ericpan

draw the schematic

flux

I’ll build a draft Route A Tier 2 schematic from the documented BOM, using the selected F1/F2/F3 parts where available and explicit placeholders for unresolved NFC, power-path, antenna-split, and CH6 details. I’ll then run a connectivity/ERC review and report every assumption that still blocks a release-ready schematic.

flux

I prepared the complete Route A Tier 2 schematic build plan, including six detector channels, selected filters, op-amps, LEDs, NFC/power paths, and provisional placeholders. No schematic objects were added because the account has no available ACUs.
Remaining work:
  • Place and wire the full draft schematic.
  • Run ERC/connectivity verification.
  • Document unresolved assumptions directly in the schematic.
Once ACUs are available, I can execute the prepared build without further requirements.
Review build assumptions
Document design decisions
Review BOM risks
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Missing Netlist Questions
Locked reconstruction target
Route A Tier 2 / A-XIAO full configuration is the first reconstruction target. Route B and Tier 1 are excluded from the first schematic. Historical v0.4 circuitry is excluded unless explicitly restored.
Questions are ordered by dependency: Priority 0 answers determine architecture and part pinouts; Priority 1 completes the electrical netlist; Priority 2 completes protection, tuning, and validation details. Answering Priority 0 first avoids rework.
Priority 0 — architecture and pinout blockers
Q1. Which exact XIAO module is the Tier 2 target?
Choose one exact product/MPN:
  • Seeed Studio XIAO ESP32-S3
  • Seeed Studio XIAO SAMD21
  • Other exact XIAO variant
Also confirm whether it is soldered directly to castellated pads or fitted using headers. This decision fixes A0–A5, SDA, SCL, 5V, GND, and wake-GPIO pin mapping and analog voltage limits.
Q2. Which exact ST25DV16K orderable part is intended?
Provide the complete MPN/package or its datasheet link. Confirm whether the intended part actually uses the source-listed SO-8 footprint. This fixes RF coil pins, EH, VCC, GND, SDA, SCL, GPO, and configuration/address pins.
Q3. Confirm the Tier 2 power-source netlist and D10–D13 roles.
Please confirm or correct this proposed interpretation:
  1. ST25DV EH output → D10 → supercapacitor/clamp node → D11 → VRAIL
  2. CR2032 positive → D12 → VRAIL
  3. XIAO 5V → D13 → VRAIL
  4. All source grounds share GND
  5. ZD1 and C_SUP connect from the intermediate NFC storage node to GND
For each diode, confirm anode and cathode. Also confirm whether D10 and D11 are intentionally both required in series.
Q4. Which exact F2 and F3 filter parts are intended? — F1 resolved
Resolved F1 decision: Mini-Circuits BFTC-500+, 50 Ω LTCC filter, 400–600 MHz, 3.81 × 3.81 mm. Pin 2 = RF IN, pin 5 = RF OUT, pins 1/3/4/6 = GND; no external matching network is required. This intentionally accepts a wider upper passband than the original 400–510 MHz target: energy from 510–600 MHz will contribute to CH3, reducing upper-band discrimination. RF-port DC-blocking capacitor(s) are required only if DC is present.
Still provide manufacturer and MPN/datasheet for:
  • F2: 698–960 MHz LTCC
  • F3: 2.4–2.5 GHz SAW
The remaining selections fix package pins, grounded terminals, input/output direction, and required external matching.
Q5. How is ANT1 electrically split into six channels?
Choose or provide the intended topology:
  • direct six-way parallel connection exactly as illustrated;
  • six branches with series coupling components;
  • a resistive splitter;
  • a distributed/microstrip splitter;
  • another topology.
If direct parallel is intended, confirm that no impedance matching or branch isolation is required for the first prototype.
Q6. Provide the CH6 microstrip BPF electrical geometry.
Required: filter topology, trace widths/lengths, gaps, feed/tap positions, layer, ground-via arrangement, solder-mask condition, and substrate dielectric assumptions. If no calculated geometry exists, confirm that CH6 should be represented in the schematic as a two-pin placeholder F4 pending EM design.
Priority 1 — complete functional connectivity
Q7. Confirm each detector diode orientation.
For D1–D6, state whether the filter output connects to the SMS7630 anode or cathode. Confirm the opposite terminal feeds the detector RC/op-amp node exactly as shown, or provide the corrected topology.
Q8. Confirm U1/U2 physical amplifier allocation.
The current logical allocation is:
  • CH1 → U1A
  • CH2 → U1B
  • CH3 → U1C
  • CH4 → U1D
  • CH5 → U2A
  • CH6 → U2B
  • U2C/U2D unused, both inputs grounded, outputs open
Confirm this allocation and the exact SGM8044 MPN/pinout. Confirm U1/U2 V+ = VRAIL and V− = GND.
Q9. Confirm the six analog output connections to XIAO.
Proposed mapping:
  • CH1 output → R51 → A0
  • CH2 output → R52 → A1
  • CH3 output → R53 → A2
  • CH4 output → R54 → A3
  • CH5 output → R55 → A4
  • CH6 output → R56 → A5
Confirm whether the bridge connects directly to the op-amp output or whether a series resistor, clamp, or divider is required. The possible output range must not exceed the selected XIAO ADC input limits.
Q10. Define the ST25DV-to-XIAO digital nets.
Confirm:
  • ST25DV SDA → XIAO SDA
  • ST25DV SCL → XIAO SCL
  • ST25DV GPO → which exact XIAO GPIO/wake pin?
  • I²C pull-up rail and resistor values
  • GPO pull-up rail and resistor value, if required
  • ST25DV I²C address/configuration pin strapping
Q11. Define ST25DV supply operation.
Confirm whether ST25DV VCC connects to VRAIL, XIAO 3V3, or another node. Clarify expected behavior when only NFC field energy is present and the XIAO is unpowered.
Q12. Define the NFC coil and tuning network.
Resolve the source conflict: 25 × 35 mm versus 15 × 24 mm. Provide or approve:
  • final outer dimensions;
  • turn count;
  • trace width and spacing;
  • layer and winding direction;
  • target inductance;
  • tuning capacitor value(s) and designators;
  • any damping/matching resistor;
  • direct pin connection to U3.
Q13. Confirm LED polarity and connection.
Proposed per channel: op-amp output → LED anode → LED cathode → 680 Ω → GND. Confirm polarity and whether the resistor may instead be placed above the LED without changing function.
Q14. Confirm decoupling and bulk capacitors.
Current source shows:
  • C61: 100 nF from U1 V+ to GND
  • C62: 100 nF from U2 V+ to GND
Confirm whether a shared VRAIL bulk capacitor is required and provide its value. Confirm whether U3 and XIAO support capacitors should be included on the carrier board.
Q15. Define the CR2032 holder and battery path.
Provide the holder MPN/footprint or mechanical dimensions. Confirm BT1 positive → D12 → VRAIL and BT1 negative → GND, with no charging path under any source combination.
Priority 2 — protection, RF tuning, and release details
Q16. What components make up the “RF matching miscellaneous passive set”?
Provide values/designators per channel, or confirm that empty tuning footprints should be added. Specify whether each footprint is series or shunt and its initial fitted/DNP state.
Q17. Should the v0.4 antenna input protection be restored?
The v0.5 BOM removed the input 100 pF DC-block capacitor and RCLAMP0524P TVS. Confirm whether ANT1 feeds the branch network directly with no ESD/DC-block component.
Q18. Confirm the CH1 LNA/load-switch deletion.
The v0.5 BOM removes PSA4-5043+, Si2302, and TPS63900, but one source note still mentions the CH1 LNA. Confirm these parts and all associated footprints are omitted from the Tier 2 reconstruction.
Q19. Confirm generic component specifications.
Provide preferred ratings/series, or approve engineering selection, for:
  • 0805 resistors: tolerance and power;
  • RF capacitors: dielectric, tolerance, and voltage;
  • inductors: tolerance, SRF, Q, and current;
  • green LEDs: MPN/brightness/Vf;
  • 5.1 V Zener: MPN and power;
  • 1 F supercapacitor: MPN, ESR, leakage, and footprint;
  • RB520S-30 exact manufacturer variant.
Q20. Are test points required?
Recommended minimum: GND, VRAIL, NFC storage node, ST25DV EH, and OUT1–OUT6. Confirm which should be included and whether they need probe loops or SMT pads.
Fastest response format
A compact response can use this form:
Text
Q1: XIAO ESP32-S3, direct castellated mounting
Q2: [exact ST25DV MPN or datasheet]
Q3: proposed power netlist accepted, except ...
Q4: F2=..., F3=... (F1=BFTC-500+ already resolved)
Q5: direct six-way parallel for prototype
Q6: represent F4 as placeholder pending EM design
...
The first six answers are sufficient to start selecting the core symbols/footprints and drafting the principal nets. Questions 7–15 are required before the schematic can be considered electrically complete.

  • Locked reconstruction target

  • Priority 0 — architecture and pinout blockers

  • Q1. Which exact XIAO module is the Tier 2 target?

  • Q2. Which exact ST25DV16K orderable part is intended?

  • Q3. Confirm the Tier 2 power-source netlist and D10–D13 roles.

  • Q4. Which exact F2 and F3 filter parts are intended? — F1 resolved

  • Q5. How is ANT1 electrically split into six channels?

  • Q6. Provide the CH6 microstrip BPF electrical geometry.

  • Priority 1 — complete functional connectivity

  • Q7. Confirm each detector diode orientation.

  • Q8. Confirm U1/U2 physical amplifier allocation.

  • Q9. Confirm the six analog output connections to XIAO.

  • Q10. Define the ST25DV-to-XIAO digital nets.

  • Q11. Define ST25DV supply operation.

  • Q12. Define the NFC coil and tuning network.

  • Q13. Confirm LED polarity and connection.

  • Q14. Confirm decoupling and bulk capacitors.

  • Q15. Define the CR2032 holder and battery path.

  • Priority 2 — protection, RF tuning, and release details

  • Q16. What components make up the “RF matching miscellaneous passive set”?

  • Q17. Should the v0.4 antenna input protection be restored?

  • Q18. Confirm the CH1 LNA/load-switch deletion.

  • Q19. Confirm generic component specifications.

  • Q20. Are test points required?

  • Fastest response format