PCB Design Help

Thought for 8 sec

Understood—I’ll treat this as a preliminary selection draft, not lock the parts into Route A Tier 2 yet. I’ll clearly flag the F2 diplexer’s unused high-band-port decision for later validation.### Preliminary replacement draft

F2 — TDK DPX162690DT-8058A1
- 698–960 MHz low-band path, 50 Ω
- 1.6 × 0.8 mm, 0603
- Pin 2 common input, pin 6 low-band output
- Pins 1, 3, 5 ground; pin 4 high-band port
- No external LC matching; use 50 Ω transmission lines
- Open issue: TDK does not specify whether unused pin 4 should be open or terminated. Confirm with TDK or prototype both configurations before locking it.
F3 — Johanson 2450BP08C0100002T
- 2400–2500 MHz, 50 Ω
- 1.1 × 0.9 × 0.45 mm
- Pin 1 input, pin 4 output
- Pins 2, 3, 5 ground
- No external matching; use 50 Ω transmission lines and close ground vias
- 1.2 dB maximum insertion loss; 12 dB minimum return loss

Draft recommendation: F3 is ready to adopt. F2 is electrically suitable and exceptionally compact, but remains provisional because it is a diplexer rather than a dedicated two-port BPF.

256ericpan

Document these preliminary F2 and F3 selections in the Route A Tier 2 BOM, keeping F2 marked provisional.

Worked for 12 sec

flux

Updated the Designator-Level BOM with both preliminary selections. F2 remains explicitly provisional pending validation of its unused high-band port; F3 includes its verified pinout and no-match requirement.

256ericpan

draw the schematic

Thought for 5 sec

flux

I’ll build a draft Route A Tier 2 schematic from the documented BOM, using the selected F1/F2/F3 parts where available and explicit placeholders for unresolved NFC, power-path, antenna-split, and CH6 details. I’ll then run a connectivity/ERC review and report every assumption that still blocks a release-ready schematic.

Worked for 30 sec

flux

I prepared the complete Route A Tier 2 schematic build plan, including six detector channels, selected filters, op-amps, LEDs, NFC/power paths, and provisional placeholders. No schematic objects were added because the account has no available ACUs.

Remaining work:

Place and wire the full draft schematic.
Run ERC/connectivity verification.
Document unresolved assumptions directly in the schematic.

Once ACUs are available, I can execute the prepared build without further requirements.

Review build assumptions

Document design decisions

Review BOM risks

No schematic yet

Talk to Flux to get started.

Designator-Level BOM

Reconstruction target decision (2026-08-12): Route A Tier 2 / A-XIAO full configuration. Route B and Tier 1 are out of scope for the first schematic reconstruction. Tier 2 includes the six parallel detector channels, LEDs, R51–R56 analog bridges, XIAO module, NFC tag/harvesting path, supercapacitor, CR2032 path, and XIAO 5 V backfeed ORing path.

Basis and precedence

This expansion uses the Route A v0.5 schematic SVG as the authoritative source for designators and values, with rf-energy-sniffer_BOM_v05.xlsx for packages and tier populations. The re-uploaded tier workbook is v0.4 and is retained only as historical comparison; its 0402 passives, SGM8042 amplifiers, SMA, LNA, TPS63900, USB-C, and five-diode power scheme were explicitly removed or changed by v0.5.

Population codes: F = fitted, DNP = not fitted, OPT = optional/selection dependent, ? = source conflict or insufficient information.

Route A — source-backed designator BOM

Table

Designator(s)	Qty	Function	Value / MPN	Package / implementation	Tier 1	Tier 2	Source status / unresolved data
ANT1	1	Wideband antenna	PCB monopole/meander, claimed 0.7–6 GHz	PCB copper	F	F	Exact geometry/feed/matching missing
C1, C2	2	CH1 filter capacitors	100 nF	0805	F	F	Voltage rating, dielectric, tolerance missing
L1, L2	2	CH1 filter inductors	220 nH	0805	F	F	SRF/Q/current/tolerance missing; value is tuning start point
C3, C4, C5	3	CH2 filter capacitors	47 pF	0805	F	F	C0G/NP0 and tolerance should be specified
L3, L4, L5	3	CH2 filter inductors	150 nH	0805	F	F	SRF/Q/current/tolerance missing; value is tuning start point
F1	1	CH3 band filter	Mini-Circuits BFTC-500+	6-SMD LTCC, 3.81 × 3.81 mm, case FR933-1	F	F	50 Ω internally matched; pin 2 RF IN, pin 5 RF OUT, pins 1/3/4/6 GND. No external matching required. Passband is 400–600 MHz rather than 400–510 MHz, so signals from 510–600 MHz will also reach CH3 and upper-band selectivity is reduced. Add RF-port DC-blocking capacitor(s) only if DC is present.
F2	1	CH4 band filter	TDK DPX162690DT-8058A1 (provisional)	6-terminal multilayer diplexer, EIA 0603, 1.6 × 0.8 mm	F	F	Provisional selection. 50 Ω low-band path covers 698–960 MHz. Pin 2 = common/input, pin 6 = low-band output, pins 1/3/5 = GND, pin 4 = unused high-band port. No external LC matching; use 50 Ω transmission lines. Datasheet does not specify whether unused pin 4 should be left open or terminated, so validate before locking the schematic.
F3	1	CH5 band filter	Johanson 2450BP08C0100002T	5-terminal ceramic SMD, 1.1 × 0.9 × 0.45 mm	F	F	Preliminary selection suitable for adoption: 50 Ω, 2400–2500 MHz, 1.2 dB max insertion loss and 12 dB min return loss. Pin 1 = input, pin 4 = output, pins 2/3/5 = GND. No external matching; use 50 Ω transmission lines and close ground vias.
F4	1	CH6 band filter	PCB microstrip BPF, 5.725–5.875 GHz	PCB copper	F	F	Exact topology and dimensions missing
D1–D6	6	Zero-bias RF detector	SMS7630-040LF	SOD-882	F	F	Pin mapping and polarity must be verified
C11–C16	6	Detector smoothing capacitors	100 pF	0805	F	F	C0G/NP0/tolerance/voltage missing
R11–R16	6	Detector loads	100 kΩ	0805	F	F	Tolerance/power rating missing
U1, U2	2	Quad video op-amps	SGM8044	TSSOP-14	F	F	Full orderable MPN and physical channel-to-pin mapping missing
R21–R26	6	Op-amp feedback resistors	30 kΩ	0805	F	F	1% recommended but not source-specified
R31–R36	6	Op-amp gain-to-ground resistors	1 kΩ	0805	F	F	1% recommended but not source-specified
LED1–LED6	6	Channel indicators	Green, Vf approximately 2 V	0805	F	F	Exact MPN, polarity, brightness/bin missing
R41–R46	6	LED current limiting	680 Ω	0805	F	F	Tolerance/power rating missing
R51–R56	6	Optional analog-output bridges	0 Ω	0805	DNP	OPT/F	Fit only when XIAO is powered and voltage-compatible
C61, C62	2	U1/U2 supply decoupling	100 nF	0805	F	F	Exact association U1/U2 implied; bulk capacitance not defined
U3	1	NFC tag / energy harvesting	ST25DV16K	Source says SO-8, unverified	DNP	F	Exact suffix/package/pinout/support circuit missing
D10–D13	4	Source ORing	RB520S-30	SOD-523	See note	F	Tier 2 fits all four; diode orientation/net roles require confirmation
D12	1 of above	Tier 1 battery isolation per v0.5 BOM	RB520S-30	SOD-523	F?	F	Conflicts with schematic labeling and tier behavior; confirm before release
ZD1	1	Rail clamp	5.1 V Zener	SOD-323	DNP	F	Exact MPN, power rating, tolerance, polarity missing
C_SUP	1	NFC burst storage	1 F / 5.5 V supercapacitor	SMD TBD	DNP	F	Exact MPN, footprint, ESR/leakage/polarity missing
BT1	1	Coin-cell holder	CR2032 holder	SMD TBD	F	F	Exact holder MPN/footprint missing
CELL1	1	Coin cell	CR2032, 3 V, 225 mAh	Off-board/fitted to BT1	OPT/F	OPT/F	External purchase; tier description conflicts on Tier 1 battery inclusion
XIAO1	1	Optional MCU module	XIAO ESP32-S3 or SAMD21	Module footprint TBD	DNP	F	Provisional designator; exact variant and pad mapping missing
L_NFC	1	NFC harvesting coil	PCB coil	PCB copper	DNP	F	Provisional designator; source conflicts: 25×35 mm versus 15×24 mm; turns/tuning missing
MH1–MH4	4	Mounting holes	M2	NPTH/PTH TBD	F	F	Present in PCB reference, absent from BOM; hole and annular-ring definition needed
PCB1	1	Main PCB	120×30 mm surfboard, 2-layer, 1.0 mm FR-4, 1 oz	Custom PCB	F	F	Exact outline is available as SVG path; fabrication stackup/tolerances still required

Route A quantity summary

Excluding PCB copper structures, mounting holes, battery, and XIAO module:

Fixed discrete/component placements before tier options: 64
Optional analog bridges R51–R56: 6
Tier 2 power/NFC additions represented above: U3, D10–D13, ZD1, C_SUP, and NFC coil

The v0.5 worksheet’s area estimate reports 50 fitted 0805 parts for Tier 1 and 56 for Tier 2. The explicit schematic expansion contains 47 non-LED 0805 passives plus 6 LEDs = 53 nominal 0805 placements when R51–R56 are included, or 47 when they are DNP. This does not reconcile exactly with the area worksheet, indicating that some “matching miscellaneous” or power-support passives remain undocumented.

Missing aggregate rows that cannot yet be assigned designators

Table

Source BOM row	Intended quantity	Why it cannot be expanded safely
RF matching miscellaneous passive set	1 set per board	No values, topology, count, or channel allocation
ST25DV support passives	Not listed	I²C pull-ups, GPO pull-up, decoupling, address/configuration, and NFC tuning parts absent
Power-path support	Not listed	No inrush/current limiting, rail bulk capacitor, discharge path, or test points specified
CH1 LNA / Si2302 load switch	Removed in v0.5	Appears only in v0.4 and one stale schematic note; excluded pending explicit reinstatement

Route B — components known, designators not source-backed

The Route B entries exist only as grouped BOM rows and block-level text. No Route B schematic or designator mapping was provided in the reviewed files, so assigning references would be invention.

Table

Component	Qty	Value / MPN	Package	Tier 3	Missing for expansion
RF switch	1	PE4250	QFN TBD	F	Exact suffix, pinout, control nets, matching, designator
Log detector	1	AD8318	QFN TBD	F	Exact suffix, support network, pin mapping, designator
MCU module	1	ESP32-S3-MINI-1	Module	F	Exact suffix/flash/antenna variant, pin allocation, designator
LDO	1	ME6211-3.3	SOT-23-5	F	Exact suffix, capacitor values, pin mapping, designator
USB-C connector	1	16-pin	TYPE-C TBD	F	MPN/footprint, CC resistors, ESD, netlist, designator
Decoupling/peripheral set	1 set	Unspecified	0805	F	Component count, values, ratings, and designators

v0.4 items intentionally excluded from the v0.5 Route A BOM

SMA connector
100 pF SMA/input DC-block capacitor
RCLAMP0524P input TVS
SGM8042 dual op-amps and 0402 passives
PSA4-5043+ CH1 LNA, LNA support network, and Si2302 load switch
TPS63900 buck-boost and its support network
Board-mounted USB-C for Route A
Fifth ORing diode D14

These should not be added unless the user explicitly chooses to restore the v0.4 architecture.

Decisions required before procurement release

Resolve the unused high-band-port treatment for provisional F2 DPX162690DT-8058A1 before locking its netlist. F3 is preliminarily selected as 2450BP08C0100002T; F1 is fixed as BFTC-500+ with its documented 400–600 MHz passband trade-off.
Select the exact XIAO and ST25DV variants.
Resolve D10–D13 connectivity and Tier 1’s fitted diode/battery behavior.
Define the NFC coil and complete its tuning/support network.
Define the RF branch/matching passive set.
Assign exact MPNs/ratings to all generic passives, LED, supercapacitor, holder, and Zener.
Provide the Route B detailed schematic before assigning its designators.

Basis and precedence
Route A — source-backed designator BOM
Route A quantity summary
Missing aggregate rows that cannot yet be assigned designators
Route B — components known, designators not source-backed
v0.4 items intentionally excluded from the v0.5 Route A BOM
Decisions required before procurement release