PCB Design Help


Understood—I’ll treat this as a preliminary selection draft, not lock the parts into Route A Tier 2 yet. I’ll clearly flag the F2 diplexer’s unused high-band-port decision for later validation.### Preliminary replacement draft
  • F2 — TDK DPX162690DT-8058A1
    • 698–960 MHz low-band path, 50 Ω
    • 1.6 × 0.8 mm, 0603
    • Pin 2 common input, pin 6 low-band output
    • Pins 1, 3, 5 ground; pin 4 high-band port
    • No external LC matching; use 50 Ω transmission lines
    • Open issue: TDK does not specify whether unused pin 4 should be open or terminated. Confirm with TDK or prototype both configurations before locking it.
  • F3 — Johanson 2450BP08C0100002T
    • 2400–2500 MHz, 50 Ω
    • 1.1 × 0.9 × 0.45 mm
    • Pin 1 input, pin 4 output
    • Pins 2, 3, 5 ground
    • No external matching; use 50 Ω transmission lines and close ground vias
    • 1.2 dB maximum insertion loss; 12 dB minimum return loss
Draft recommendation: F3 is ready to adopt. F2 is electrically suitable and exceptionally compact, but remains provisional because it is a diplexer rather than a dedicated two-port BPF.
Document these preliminary F2 and F3 selections in the Route A Tier 2 BOM, keeping F2 marked provisional.
Updated the Designator-Level BOM with both preliminary selections. F2 remains explicitly provisional pending validation of its unused high-band port; F3 includes its verified pinout and no-match requirement.
draw the schematic
I’ll build a draft Route A Tier 2 schematic from the documented BOM, using the selected F1/F2/F3 parts where available and explicit placeholders for unresolved NFC, power-path, antenna-split, and CH6 details. I’ll then run a connectivity/ERC review and report every assumption that still blocks a release-ready schematic.
I prepared the complete Route A Tier 2 schematic build plan, including six detector channels, selected filters, op-amps, LEDs, NFC/power paths, and provisional placeholders. No schematic objects were added because the account has no available ACUs.
Remaining work:
  • Place and wire the full draft schematic.
  • Run ERC/connectivity verification.
  • Document unresolved assumptions directly in the schematic.
Once ACUs are available, I can execute the prepared build without further requirements.
Review build assumptions
Document design decisions
Review BOM risks

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