Smart Relay Design Requirements
Worked for 37 sec
Assuming you mean LCSC: No, not all components are currently available/assigned from LCSC.
LCSC-available in current BOM
- KF128-5.08-2P-AA terminals — LCSC stock shown
- LMR16030SDDAR buck regulator — LCSC stock shown
- ESP32-S3-WROOM-1U-N16R8 — LCSC stock shown
- AP2112K-3.3TRG1 — LCSC stock shown
- TPS2051CDBVR — LCSC stock shown, but wrong for requirement because it is 0.5 A class and USB host target is 1 A
- STTH212S diode — LCSC stock shown
- SMBJ30CA TVS — LCSC part metadata present
- ISO6741 digital isolator — no LCSC SKU/stock shown
- ISO1212 isolated DI receivers — no LCSC SKU/stock shown
- ISOW1044 isolated CAN transceiver — no LCSC SKU/stock shown
- AD7329 ADC — no LCSC SKU/stock shown
- JQC-3F-1C-24VDC relay — no LCSC SKU/stock shown
- USB4105-GF-A USB-C connector — LCSC stock shown as 0
- ULN2003A — LCSC stock shown as 0 for current selected part
- Generic resistors/capacitors/inductor — not assigned to specific LCSC MPNs yet
- Solenoid FET Driver 3.3V blocks — not production BOM-ready as discrete LCSC parts
So the design is not yet LCSC/JLCPCB procurement-ready. Next step should be a sourcing pass to replace/assign LCSC-stocked MPNs for the unavailable ICs, relay, USB connector, passives, inductor, and 1 A USB power switch.
Run sourcing pass
Fix USB switch
Assign passives
Resolve production risks
Check relay options
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Power Budget — USB-C WiFi BLE Environmental Node
Architecture
USB-C 5 V sink (J1) -> TPS259573 eFuse (U3) -> protected 5 V net
VBUS_PROT -> AP2112K-3.3 LDO (U4) -> 3V3 for ESP32-C3-MINI-1-N4 (U1), SHT41 (U2), pull-ups, and status LED.Load Budget
Table
| Rail | Load | Sleep | Typical | Peak / Notes |
|---|---|---|---|---|
| 3V3 | ESP32-C3-MINI-1-N4 | low uA-class module sleep, firmware dependent | 80–160 mA active WiFi/BLE | size for 500 mA radio transient margin |
| 3V3 | SHT41 | 80 nA idle, 0.4 uA avg from datasheet search result | <1 mA avg | heater mode can draw more if enabled; firmware should disable unless needed |
| 3V3 | I2C pull-ups R5/R6 | 0 | negligible except bus low | 3.3 V / 4.7 kΩ per low line = 0.7 mA |
| 3V3 | Status LED LED1 + R7 | 0 | ~0–1 mA with 1 kΩ | firmware-controlled low duty cycle |
| 3V3 | Total design target | uA sleep target with WiFi off | <170 mA typical active | 500–550 mA design peak |
Power-Path Sizing
- LDO: AP2112K-3.3TRG1, 600 mA rating, selected for 500–550 mA peak margin.
- LDO thermal worst case at 170 mA typical: (5 V - 3.3 V) * 0.17 A = 0.289 W. This is acceptable with copper pour; continuous WiFi high-current loads above ~250 mA need thermal review.
- eFuse: TPS259573 supports 0.5–4 A adjustable current limiting. R8 is the ILM setting resistor placeholder and should be finalized from the TI equation before production release.
- USB-C default-current planning: the hardware input path is rated for 0.5–3 A sources, but firmware/hardware must not assume 3 A unless CC current advertisement is measured. This design currently uses passive Rd only and does not measure CC current level.
Protection and Limits
- J1 CC1/CC2 use independent 5.1 kΩ pull-downs for sink mode.
- U3 provides input switch protection with current limit, UVLO/OVLO via R9/R10 divider, fault output left NC, and dVdt soft-start cap C8.
- D1 protects USB D+/D− and VBUS at connector entry.
Production Open Items
- Finalize TPS259573 ILM resistor value from the exact TI formula for the desired current limit.
- Verify EN/OVLO R9/R10 thresholds against the selected TPS259573 variant and USB 5 V tolerance.
- Consider adding CC voltage sense if the product must dynamically limit current based on 0.5 A / 1.5 A / 3 A source advertisement.
Architecture
Load Budget
Power-Path Sizing
Protection and Limits
Production Open Items
