• Terminal
    Terminal
    An electrical connector acting as reusable interface to a conductor and creating a point where external circuits can be connected.
  • Ground
    A common return path for electric current. Commonly known as ground.
  • Net Portal
    A net identifier used to create connectivity to other Net Portal with the same designator. #portal
  • Power Net Portal
    Power net portal is a special schematic object used to define a power or ground net. Power ports allow you to conveniently indicate a power net at any location in the design. Power nets of the same designator automatically connect throughout your design #portal #power
  • Generic Resistor
    A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibrary
  • Generic Capacitor
    A generic fixed capacitor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard capacitor values: 1.0pF 10pF 100pF 1000pF 0.01uF 0.1uF 1.0uF 10uF 100uF 1000uF 10,000uF 1.1pF 11pF 110pF 1100pF 1.2pF 12pF 120pF 1200pF 1.3pF 13pF 130pF 1300pF 1.5pF 15pF 150pF 1500pF 0.015uF 0.15uF 1.5uF 15uF 150uF 1500uF 1.6pF 16pF 160pF 1600pF 1.8pF 18pF 180pF 1800pF 2.0pF 20pF 200pF 2000pF 2.2pF 22pF 20pF 2200pF 0.022uF 0.22uF 2.2uF 22uF 220uF 2200uF 2.4pF 24pF 240pF 2400pF 2.7pF 27pF 270pF 2700pF 3.0pF 30pF 300pF 3000pF 3.3pF 33pF 330pF 3300pF 0.033uF 0.33uF 3.3uF 33uF 330uF 3300uF 3.6pF 36pF 360pF 3600pF 3.9pF 39pF 390pF 3900pF 4.3pF 43pF 430pF 4300pF 4.7pF 47pF 470pF 4700pF 0.047uF 0.47uF 4.7uF 47uF 470uF 4700uF 5.1pF 51pF 510pF 5100pF 5.6pF 56pF 560pF 5600pF 6.2pF 62pF 620pF 6200pF 6.8pF 68pF 680pF 6800pF 0.068uF 0.68uF 6.8uF 68uF 680uF 6800uF 7.5pF 75pF 750pF 7500pF 8.2pF 82pF 820pF 8200pF 9.1pF 91pF 910pF 9100pF #generics #CommonPartsLibrary
  • Generic Inductor
    A generic fixed inductor for rapid developing circuit topology. *You can now change the footprint and 3D model at the top level anytime you want. This is the power of #generics
  • RMCF0805JT47K0
    47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlink
  • 875105359001
    10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcan
  • CTL1206FYW1T
    Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlink
what configurator should i conenct?

please connect all
1y
@copilot what configurator should i conenct?
1y
In order to program your ICE40UP5K-SG48I FPGA, you'd typically use a JTAG or SPI interface. The ICE40UP5K-SG48I does natively support SPI configuration which utilises the following pins:
  • IOB_32A_SPI_SO: SPI Data out
  • IOB_34A_SPI_SCK: SPI Clock
  • IOB_35B_SPI_SS: SPI Chip Select
  • IOB_33B_SPI_SI_1 and IOB_33B_SPI_SI_2: SPI data in (You can choose to use IOB_33B_SPI_SI_1 or IOB_33B_SPI_SI_2 based on your design requirement)
For JTAG configuration, the ICE40UP5K-SG48I uses four standard JTAG signals which aren't individually broken out onto separate pins in the SG48 package.
Other critical pins for configuration are:
  • CDONE: This is an output pin which when HIGH indicates configuration is done.
  • CRESET_B: An active-low reset pin for configuration.
You could connect these to appropriate pins on your microcontroller or a standard SPI/JTAG interface tool.
If you are planning to use a particular configurator, please let me know so I could be more specific on pin connections or any additional requirements.
1y
please connect all
1y
Sure, here are the connections you need to make to connect the FPGA for SPI programmability:
  1. Connect IC1:IOB_32A_SPI_SO to your microcontroller SPI:MISO (Master In Slave Out). This is the signal from FPGA to MCU.
  2. Connect IC1:IOB_34A_SPI_SCK to your MCU's SPI:SCK. This is the clock signal for the SPI interface and it synchronizes data transfer between the devices.
  3. Connect IC1:IOB_35B_SPI_SS to your MCU's SPI:CS (Chip Select). This signal enables the FPGA when your MCU wishes to communicate with it.
  4. Connect IC1:IOB_33B_SPI_SI_1 (or IC1:IOB_33B_SPI_SI_2) to your MCU's SPI:MOSI (Master Out Slave In). This is the data signal from the MCU to the FPGA.
To ensure correct operation after configuration, connect the CDONE pin to an input of your microcontroller, allowing the MCU to verify if configuration was successful. Also, connect the CRESET_B to a reset signal source in your system or to a reset button.
Bear in mind, the FPGA's power supply requirements also need to be fulfilled. Depending on your power setup, you may need to connect VCCPLL_1, VCCPLL_2, etc., to the appropriate voltage source. Do not forget the Ground pin connection, IC1:GND to the common ground of your circuit.
These connections will allow you to perform SPI configuration on the ICE40UP5K-SG48I FPGA. Please, ensure that your MCU has the necessary programming for performing the SPI configuration on the FPGA.
Remember, these are typical connections assuming a common setup, you'd need to adjust based on the specifics of your circuit.
1y
Check that none of the unconnected pins require pull-up or pull-down resistors t...

@copilot Check that none of the unconnected pins require pull-up or pull-down resistors to ensure proper function.
1y
The FPGA IC ICE40UP5K-SG48I that you have in your project generally has internal pull-up resistors that can be optionally enabled within the FPGA logic. However, the specific requirement of external pull-up or pull-down resistors can depend on the logic and inputs of your specific design.
Typically, certain pins such as the reset pin (CRESET_B) would need a pull-up resistor to ensure it remains inactive unless explicitly driven low. Similarly, the Done pin (CDONE) from your FPGA may also require a pull-up resistor to ensure the FPGA initializes properly upon power-up. The SPI bus (IOB_32A_SPI_SO, IOB_34A_SPI_SCK, IOB_35B_SPI_SS, and IOB_33B_SPI_SI_1) typically utilizes pull-up resistors in many designs to maintain a known state when the bus is not active.
Please note that this is common practice and you should refer to the specific datasheet of the IC (or the specific modules you are using inside the FPGA) to confirm if pull-up or pull-down resistors are required.
I would suggest that you review the datasheet for this chip again to confirm the behavior of each unconnected pin and check whether it needs to be pulled up or down for proper operation. Let me know if you need additional assistance.
1y
can you do it?
1y
Apologies for any confusion. Based on standardized practices and the behavior of the ICs you're using, valuable insights and recommendations can be provided. However, it's essential to note that direct readings of datasheets or specific chip information aren't possible. It can't be automatically identified which pins on your IC require pull-up or pull-down resistors as this largely depends on your specific use case, design, and the designer's decision as well.
Accurate and detailed information is usually provided in the datasheet by the manufacturer. Therefore, for precise details, please refer to the datasheet of the ICE40UP5K-SG48I chip from Texas Instruments.
Generally speaking, your focus should be on the CRESET_B pin (this is typically active low, and you may want to add a pull-up resistor to keep the chip out of reset state until you actively drive it low) and the SPI bus pins (pull-up resistors can provide known states when the bus is not active). However, it's recommended to always reference the specific requirements from your datasheet.
Do ask if assistance is required in interpreting the datasheet once you have it to hand.
1y
2

Grim Rose Massive Robot Spider

Grim Rose Massive Robot Spider
Description

Created
January 28th 2024
Last updated by ziondido
a year ago
1 Contributor(s)
ziondido

Controls

Properties

Availability & Pricing

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    Hi! I’m copilot. Think of me like an experienced electrical engineer that can he...
    Hi! I’m copilot. Think of me like an experienced electrical engineer that can help you brainstorm ideas, debug problems, research components, and even make wiring connections for you. Ask me questions like:
    • @copilot I'm designing a PCB for a medical device that measures heart rate and temperature. Can you give me the list of components I will need?
    • @copilot How would I connect these parts to make the LED flash at 1kHz?
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    Checks that the power traveling across a given resistor is under its rating with 50% headroom.
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    Checks that IC pins that require pull up or pull down resistors have them.
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    Checks that capacitors have appropriate voltage ratings to prevent overheating and ensure reliable circuit operation.
    Checks that all parts have a part number and are available from distributors.
    Reports copper elements that are shorting.
    Reports parts that have no footprint.
    Reports nodes that are assigned to a layer that doesn't exist in the layout stackup.
    Reports components that have been modified using the "!important" flag.
    Reports terminals that are not connected properly. NOTE: Only connections to the center of pads are considered valid.
    Reports nodes that are using rules that are not supported anymore.
    Reports layers that have multiple copper fills of different nets. Make sure the Connected Layers rule value of nets with fills is valid.
    Detect any via, trace or copper fill island that is not connected to any net.