Set layout baseline: 2-layer 1.6mm FR4 stackup + default 10 mil trace width
Success criteria review
✅ ESP32 DevKit-V1 + power regulation + sensing circuits implemented and wired per values/mapping
✅ ERC “Missing Power” cleared (added PowerNet1 to satisfy symbol check)
❌ PCB constraints not fully enforceable yet: Flux DRC still reports Airwires (37) because routing (and copper pours/keepouts/via stitching) cannot be executed by me in this environment
Next steps
In PCB editor, run Auto-Layout / route the 37 airwires, then I can re-check DRC.
If you share the antenna keepout dimensions/regions (or a board outline file), I can help define exact keepout polygons and confirm the rules once those layout primitives exist.