Schematic Design Assistance


Read-only verification completed; I did not modify the schematic.

Table


ESP32-C3 pinNet nameConnected component pins on that net
GPIO3IRQ_SHARED_GPIO3U1:GPIO3, U2:IRQ, U5:~{INT}
GPIO4I2C_SDA_GPIO4U1:GPIO4, U2:SDA, U3:SDA, U4:SDA_OUT, U5:SDA, OLED1:SDA, R6:P2
GPIO5I2C_SCL_GPIO5U1:GPIO5, U2:SCL, U3:SCL, U4:SCL_OUT, U5:SCL, OLED1:SCL, R7:P2
GPIO6RGB_DATA_GPIO6U1:GPIO6, R21:P1
GPIO7FP_TOUCHOUT_GPIO7U1:GPIO7, J1:8
GPIO8STATUS_LED_GPIO8U1:GPIO8
GPIO10GPIO10_SPARE_TPU1:GPIO10
GPIO20FP_UART_TX_TO_ESP_RX_GPIO20U1:GPIO20, J1:5
GPIO21FP_UART_RX_FROM_ESP_TX_GPIO21U1:GPIO21, J1:4
3V33V3U1:3V3, U2:VDD, U2:ADDR, U3:VDD, U3:VDD_NC, U3:EN, U4:3.3v power, U4:RESET, U5:VCC, J1:6, J1:7, LED1:VDD, LED2:VDD, LED3:VDD, LED4:VDD, OLED1:5V, R6:P1, R7:P1, R22:P1, R23:P1, R24:P1, R25:P1, R26:P1, C5:P1, C7:P1, C9:P1, C10:P1, C11:P1, C12:P1, C13:P1, C14:P1
GNDGNDU1:GND, U2:VSS, U3:GND, U4:SPGND, U5:GND, U5:A0, U5:A1, U5:A2, J1:1, J1:2, J1:9, J1:10, J1:11, J1:12, LED1:GND, LED2:GND, LED3:GND, LED4:GND, OLED1:GND, SW1:P2, SW2:P2, SW3:P2, SW4:P2, R8:P2, C5:P2, C6:P2, C7:P2, C8:P2, C9:P2, C10:P2, C11:P2, C12:P2, C13:P2, C14:P2
Confirmations:
  1. ✅ Fingerprint FPC J1:5 UART_TX connects to ESP GPIO20; J1:4 UART_RX connects to ESP GPIO21.
  2. ⚠️ Fingerprint OTP J1:3 is isolated from MCU/other circuitry, but current netlist shows only J1:3 on FP_OTP_TP_ONLY; I do not see a test pad connected.
  3. ✅ MPR121 ADDR is tied to 3V3.
  4. ⚠️ BNO055 ADR cannot be verified from this selected BNO055 sublayout; no ADR pin is exposed. Address-low/open is therefore an assumption, not netlist-confirmed.
  5. ⚠️ MPR121 IRQ and TCA9534A ~INT share IRQ_SHARED_GPIO3 to ESP GPIO3, but I do not see an external pullup on that IRQ net.
Please fix exactly these two issues and nothing else: 1) Add a test pad component on net FP_OTP_TP_ONLY so fingerprint OTP J1:3 has an actual test pad, as originally specified. 2) Add a 10 kOhm pullup resistor from net IRQ_SHARED_GPIO3 to 3V3, since MPR121 IRQ and TCA9534A INT are open-drain and the line currently has no pullup. Do not change any GPIO assignments, nets, or other components. BNO055 ADR is fine as-is (module handles addressing internally). After the fixes, re-run ERC and confirm both changes.
I’ll make only those two schematic fixes: add an OTP test pad to FP_OTP_TP_ONLY and add a 10 kΩ pullup from IRQ_SHARED_GPIO3 to 3V3, then rerun ERC.
Done — made only the two requested schematic changes.
Confirmed:
  • Added TP37 to fingerprint OTP net FP_OTP_TP_ONLY; it is associated with J1:3 / OTP test-only connectivity.
  • Added R31 = 10kΩ pullup:
    • R31:P13V3
    • R31:P2IRQ_SHARED_GPIO3
    • IRQ_SHARED_GPIO3 contains U1:GPIO3, U2:IRQ, U5:~{INT}, and R31:P2.
ERC re-run result: no ERROR, WARNING, or OPEN checks returned.
Review, document, layout
Run schematic review
Update project notes
Start PCB placement
Check BOM availability

LED4
LED1
LED3
LED2
U4
U2
C13
Capacitance
10uF
C16
Capacitance
Capacitance
C14
Capacitance
0.1uF
C15
Capacitance
Capacitance
C6
Capacitance
0.1uF
C8
Capacitance
1.0uF
C10
Capacitance
0.1uF
C7
Capacitance
0.1uF
C12
Capacitance
100uF
C5
Capacitance
0.1uF
C9
Capacitance
0.1uF
C11
Capacitance
0.1uF
OLED1
TP32
TP23
TP3
TP9
TP4
TP18
TP11
TP14
TP20
TP7
TP5
TP10
TP29
TP17
TP21
TP15
TP30
TP37
TP35
TP13
TP8
TP12
TP24
TP6
TP19
TP34
TP22
TP1
TP25
TP36
TP31
TP2
TP26
TP28
TP33
TP27
TP16
J2
R18
Resistance
R17
Resistance
R22
Resistance
1.0kΩ
R14
Resistance
R15
Resistance
R20
Resistance
R7
Resistance
4.7kΩ
U3
R27
Resistance
500 Ω
R25
Resistance
10kΩ
R10
Resistance
R11
Resistance
R31
Resistance
10kΩ
R29
Resistance
500 Ω
R24
Resistance
10kΩ
R6
Resistance
4.7kΩ
R8
Resistance
75kΩ
R12
Resistance
R23
Resistance
10kΩ
R19
Resistance
R30
Resistance
500 Ω
R28
Resistance
500 Ω
R26
Resistance
10kΩ
R13
Resistance
R21
Resistance
330Ω
R9
Resistance
R16
Resistance
U1
SW4
SW1
SW2
SW3
J1
U5
D1

BlackStar_Remote_V0

BlackStar_Remote_V0 thumbnail