Schematic Design Assistance

Thought for 42 sec

Read-only verification completed; I did not modify the schematic.

Table

ESP32-C3 pin	Net name	Connected component pins on that net
GPIO3	`IRQ_SHARED_GPIO3`	`U1:GPIO3`, `U2:IRQ`, `U5:~{INT}`
GPIO4	`I2C_SDA_GPIO4`	`U1:GPIO4`, `U2:SDA`, `U3:SDA`, `U4:SDA_OUT`, `U5:SDA`, `OLED1:SDA`, `R6:P2`
GPIO5	`I2C_SCL_GPIO5`	`U1:GPIO5`, `U2:SCL`, `U3:SCL`, `U4:SCL_OUT`, `U5:SCL`, `OLED1:SCL`, `R7:P2`
GPIO6	`RGB_DATA_GPIO6`	`U1:GPIO6`, `R21:P1`
GPIO7	`FP_TOUCHOUT_GPIO7`	`U1:GPIO7`, `J1:8`
GPIO8	`STATUS_LED_GPIO8`	`U1:GPIO8`
GPIO10	`GPIO10_SPARE_TP`	`U1:GPIO10`
GPIO20	`FP_UART_TX_TO_ESP_RX_GPIO20`	`U1:GPIO20`, `J1:5`
GPIO21	`FP_UART_RX_FROM_ESP_TX_GPIO21`	`U1:GPIO21`, `J1:4`
3V3	`3V3`	`U1:3V3`, `U2:VDD`, `U2:ADDR`, `U3:VDD`, `U3:VDD_NC`, `U3:EN`, `U4:3.3v power`, `U4:RESET`, `U5:VCC`, `J1:6`, `J1:7`, `LED1:VDD`, `LED2:VDD`, `LED3:VDD`, `LED4:VDD`, `OLED1:5V`, `R6:P1`, `R7:P1`, `R22:P1`, `R23:P1`, `R24:P1`, `R25:P1`, `R26:P1`, `C5:P1`, `C7:P1`, `C9:P1`, `C10:P1`, `C11:P1`, `C12:P1`, `C13:P1`, `C14:P1`
GND	`GND`	`U1:GND`, `U2:VSS`, `U3:GND`, `U4:SPGND`, `U5:GND`, `U5:A0`, `U5:A1`, `U5:A2`, `J1:1`, `J1:2`, `J1:9`, `J1:10`, `J1:11`, `J1:12`, `LED1:GND`, `LED2:GND`, `LED3:GND`, `LED4:GND`, `OLED1:GND`, `SW1:P2`, `SW2:P2`, `SW3:P2`, `SW4:P2`, `R8:P2`, `C5:P2`, `C6:P2`, `C7:P2`, `C8:P2`, `C9:P2`, `C10:P2`, `C11:P2`, `C12:P2`, `C13:P2`, `C14:P2`

Confirmations:

✅ Fingerprint FPC J1:5 UART_TX connects to ESP GPIO20; J1:4 UART_RX connects to ESP GPIO21.
⚠️ Fingerprint OTP J1:3 is isolated from MCU/other circuitry, but current netlist shows only J1:3 on FP_OTP_TP_ONLY; I do not see a test pad connected.
✅ MPR121 ADDR is tied to 3V3.
⚠️ BNO055 ADR cannot be verified from this selected BNO055 sublayout; no ADR pin is exposed. Address-low/open is therefore an assumption, not netlist-confirmed.
⚠️ MPR121 IRQ and TCA9534A ~INT share IRQ_SHARED_GPIO3 to ESP GPIO3, but I do not see an external pullup on that IRQ net.

yari4embedded

Please fix exactly these two issues and nothing else: 1) Add a test pad component on net FP_OTP_TP_ONLY so fingerprint OTP J1:3 has an actual test pad, as originally specified. 2) Add a 10 kOhm pullup resistor from net IRQ_SHARED_GPIO3 to 3V3, since MPR121 IRQ and TCA9534A INT are open-drain and the line currently has no pullup. Do not change any GPIO assignments, nets, or other components. BNO055 ADR is fine as-is (module handles addressing internally). After the fixes, re-run ERC and confirm both changes.

Thought for 6 sec

flux

I’ll make only those two schematic fixes: add an OTP test pad to FP_OTP_TP_ONLY and add a 10 kΩ pullup from IRQ_SHARED_GPIO3 to 3V3, then rerun ERC.

Worked for 1 min 42 sec

flux

Done — made only the two requested schematic changes.

Confirmed:

Added TP37 to fingerprint OTP net FP_OTP_TP_ONLY; it is associated with J1:3 / OTP test-only connectivity.
Added R31 = 10kΩ pullup:
- R31:P1 → 3V3
- R31:P2 → IRQ_SHARED_GPIO3
- IRQ_SHARED_GPIO3 contains U1:GPIO3, U2:IRQ, U5:~{INT}, and R31:P2.

ERC re-run result: no ERROR, WARNING, or OPEN checks returned.

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Schematic

Layout

Preview

LED4

LED1

LED3

LED2

OLED1

R18

Resistance

0Ω

R17

Resistance

0Ω

R22

Resistance

1.0kΩ

R14

Resistance

0Ω

R15

Resistance

0Ω

R20

Resistance

0Ω

Resistance

4.7kΩ

R27

Resistance

500 Ω

R25

Resistance

10kΩ

R10

Resistance

0Ω

R11

Resistance

0Ω

R31

Resistance

10kΩ

R29

Resistance

500 Ω

R24

Resistance

10kΩ

Resistance

4.7kΩ

Resistance

75kΩ

R12

Resistance

0Ω

R23

Resistance

10kΩ

R19

Resistance

0Ω

R30

Resistance

500 Ω

R28

Resistance

500 Ω

R26

Resistance

10kΩ

R13

Resistance

0Ω

R21

Resistance

330Ω

Resistance

0Ω

R16

Resistance

0Ω

C13

Capacitance

10uF

TP32

TP23

TP3

TP9

TP4

TP18

TP11

TP14

TP20

TP7

TP5

C16

Capacitance

TP10

TP29

C14

Capacitance

0.1uF

TP17

TP21

C15

Capacitance

TP15

TP30

Capacitance

0.1uF

TP37

TP35

TP13

TP8

TP12

Capacitance

1.0uF

TP24

TP6

TP19

TP34

TP22

TP1

TP25

TP36

C10

Capacitance

0.1uF

TP31

Capacitance

0.1uF

TP2

C12

Capacitance

100uF

Capacitance

0.1uF

TP26

Capacitance

0.1uF

TP28

TP33

C11

Capacitance

0.1uF

TP27

TP16

SW4

SW1

SW2

SW3

BlackStar Remote V0 — Schematic Notes

Scope

Schematic-only prototype implementation. PCB placement/routing intentionally not started.

Controller GPIO Plan

GPIO4: I2C SDA
GPIO5: I2C SCL
GPIO3: shared open-drain IRQ from MPR121 and TCA9534A INT
GPIO20: ESP RX from fingerprint UART_TX
GPIO21: ESP TX to fingerprint UART_RX
GPIO7: fingerprint TOUCHOUT input
GPIO6: RGB ring SK6812 data via 330 Ω series resistor
GPIO8: onboard/status LED test pad only
GPIO10: spare/test pad
GPIO18/GPIO19 not used; GPIO9 marked NC/not used for user buttons.

Major Components

U1: ESP32-C3 SuperMini SMD module
U2: custom MPR121QR2 component created from NXP datasheet, 20-QFN 3 × 3 mm, 0.4 mm pitch
U3: DRV2605LDGST haptic driver
U4: BNO055 I2C 3.3 V module/sublayout
U5: TCA9534APWR GPIO expander
J1: Molex 5052781233 12-pin 0.5 mm bottom-contact FPC for Q Tech F6B27_C fingerprint sensor
LED1–LED4: SK6812MINI-E RGB LEDs
OLED1: optional SSD1306 I2C OLED module, DNI

Address / Bus Assumptions

MPR121 ADDR tied to 3V3 for 0x5B.
DRV2605L expected at 0x5A.
BNO055 expected at 0x28.
Optional SSD1306 OLED expected at 0x3C.
TCA9534A A0/A1/A2 tied low for 0x20.
Only one effective I2C pullup set installed: R6/R7 = 4.7 kΩ to 3V3.

Fingerprint FPC Mapping

J1 follows requested F6B27_C 12-pin mapping: 1 GND, 2 GND, 3 OTP test pad only, 4 UART_RX from ESP GPIO21, 5 UART_TX to ESP GPIO20, 6 VCC3V3, 7 VDDS, 8 TOUCHOUT to ESP GPIO7, 9–12 GND.

MPR121 Electrode Mapping

R9–R20 are 0 Ω/debug isolation jumpers:

E0 Up
E1 Upper-right
E2 Right
E3 Lower-right
E4 Down
E5 Lower-left
E6 Left
E7 Upper-left
E8–E11 spare/test pads

Layout note: keep copper/ground pour away from touch electrode pads/traces and use guard/clearance strategy during PCB layout.

Open Mechanical / Footprint Checks

Verify Q Tech F6B27_C flex pitch, contact side, stiffener orientation, and required FPC connector contact orientation before PCB layout.
Confirm OLED module supply tolerance if OLED1 is populated; current schematic connects its module pin named 5V to 3V3 to preserve 3.3 V-only prototype operation.
Confirm haptic motor type/current against DRV2605L mode and JST-PH connector/cable choice.

BOM Suggestions

MPR121QR2: custom part from NXP datasheet; note MPR121 appears archived/discontinued, so availability risk exists.
FPC: Molex 5052781233, 12-position 0.5 mm bottom-contact right-angle SMT.
RGB: SK6812MINI-E preferred for 3.3 V data compatibility.
Button pullups R23–R26 may be DNI if firmware enables reliable TCA9534A/internal pullups or alternate expander pullups.

Firmware Bring-up Notes

Confirm 3V3 rail current headroom before enabling RGB full-white.
Scan I2C for 0x20, 0x28, 0x5A, 0x5B, and optional 0x3C.
Configure GPIO3 as input with pullup if required; both MPR121 IRQ and TCA9534A INT are open-drain/shared.
Configure fingerprint UART on GPIO20/GPIO21 and verify TOUCHOUT on GPIO7.
Initialize SK6812 on GPIO6 at conservative brightness.

Scope
Controller GPIO Plan
Major Components
Address / Bus Assumptions
Fingerprint FPC Mapping
MPR121 Electrode Mapping
Open Mechanical / Footprint Checks
BOM Suggestions
Firmware Bring-up Notes