I couldn’t produce a faithful schematic PDF: the available PDF export covers PCB layers only, and the schematic-rendering fallback loses symbol detail. No PDF was created, and your design is unchanged.
I’ll make a cosmetic-only readability pass using the ten requested blocks, left-to-right signal flow and inter-block net labels. I’ll compare the complete netlist, parts and values before and after, and won’t touch PCB layout.
Thought for 1 min 53 sec
10 hrs ago
Thought for 7 sec
1/3 Capture baseline component/value inventory and complete netlist invariants
Capture baseline component/value inventory and complete netlist invariants
Arrange ten schematic blocks and clean cosmetic wiring/labels without electrical changes
Compare before/after netlist and visually check readability; stop without PCB layout
Thought for 42 sec
Awaiting 1 task
"Schematic Readability Pass" completed.
Thought for 59 sec
flux
10 hrs ago
The readability pass is blocked: my available controls do not support schematic canvas placement, frames, or graphical wire/net-label editing, so I made no changes.
Before: 328 components / 188 nets.
After inspection: 328 components / 188 nets.
Parts, values and connectivity remain untouched; no PCB layout started.
I cannot claim the rearrangement or a full before/after netlist comparison was completed. This limitation needs Contact Support.
Controls over prior inventory/direct-PWM descriptions below: independent review's partial-power defect corrected by U6 SN74LVC1T45DBVT dual-supply translator (VCCA3V3/VCCB5V/DIR3V3), R23=10k output pulldown and C10/C11=100nF decouplers. Manufacturer Ioff protection and either-supply-atGND high-Z support safe missing-rail interface without firmware-dependent injection limiting. SHUTDOWN_RELAY_PULSE remains3V3 boundary withTP4/R2; SHUTDOWN_PUMP_INPUT_5V is new internalU6B→IC1IN_A/R23 node. Existing capacitive pulse-energy, direct cutoff, health/power supervision and floating output unchanged; intermediate ramps still require bench validation.
Latest 54components/14types,25nets,122logicalmemberships,12TPs,6NCs. TP4 corrected40kHz50%duty;TP8 namesQ3 notremovedQ2. C9 exactMPN/effectivebias-C order-stage; AQY212 pins1/2 LED known but polarity not independently resolved by indexed drawing, no rewiring. TargetedERC4Errors/1Warning: IC1IN_A now physicalU6Bdriver/checker-port-semantics,IN_Bground-source semantics,VDD/GND future real sources,D1libraryWarning.97unroutedairwires/missingfootprintsnone; noPCB changes/simulation/secondindependentreview. Newpartsawaitlaterplacement. Benchcurrent/capacitor/timing/thermal/leakage/isolationtests remainuser-acceptedunattempted. See latest addenda in project files shutdown-design-notes and shutdown-focused-review; userpausewaived,lead proceedsBlock2separately.
Controlling shutdown revision — 2026-10-10
This section supersedes all older shutdown active-dump topology, passive values/inventory, fixed5mA acceptance, simulation acceptance and review-pause statements elsewhere in this document. Other subsystem requirements remain unchanged. The latest shutdown review was read in full and implemented. The user's later “After this proceed to the next step without review” waives the user-review pause: the lead will inspect this revised Block1 and continue Block2 power entry/supervision in a separate scope without another confirmation. Professional EE/bench qualification remains required; layout/order approval is not granted. This worker built ONLY shutdown revisions.
**Actual current Block1:**50components/13unique types,24namednets,110logicalpinmemberships,12connectedtestpoints,6intentionalNCs. Removeddump-onlyQ1/Q2/R7/R8/R10/R19/R20 andall4dumpnets; keptQ3directseriesLEDcutoff,independenthealthtimerandlocalrail/MRsupervision. IC1Aalonebufferspump; unusedIN_Bgrounded/OUT_BNC. Nooutputreadback.
**Prototype values/firmware:**R1=180ohm1%0.5W0805 retained;R9=22ohm1%1.5W2512 CRCW251222R0FKEGHP(existingpackage retained);C1=1uF50V1206 SamsungCL31B105KBHNNNE;C8=1uF50V0805 TDKC2012X7R1H105K125AB;R11=10kohm1%;RELAY_PULSE=40kHz50%duty. Future firmware MUST stopRELAY_PULSEontrip/disarm/notready;firmwareisnotbuilt. Q3opensLEDwithoutwaitingforreservoirdecay. Active discharge is NO LONGER required. Typical sizing targetLED5–10mA/pumpRMSorabsoluteaverage tensofmA; handequations/assumptions in shutdown-design-notes,notguaranteedwaveforms. ContinuousPWMwhileinhibitedmust be fault-tested onbench; no measuredresult claimed.
**Release:**R5=2.2kohm1%defaultpulldown. Two70kohmminimumMRinternalpullups make35kohmequivalent;MR=0.7VDD. LaterTeensy/reset/upload/all-required-railhardware must defaultinhibit; GPIOhigh-Zalone doesnotproveactualintegration/backpowerbehavior.
**LED acceptance:minimum1.5xAQY212SmaximumIFon=1.5x3mA=4.5mA;IFonmax3mAatIL=Max/25C. RecommendedIF5–30mA andToff0.2msmaxatIF5mA/IL=Max/25Careseparatetestconditions. MinimumLEDdriveand=4.5mA,command2.4 V /low <0.8 V acceptance values remain provisional until controller documentation confirms them.
Use a low-leakage bidirectional TVS directly across the floating contact pair, not to local ground or chassis. Define surge amplitude, waveform/source impedance, wrong-BNC energy, temperature and parasitic inductance before asserting coordinated protection.
An off-board insulated panel BNC with supported wiring is acceptable. Exact connector suffix, insulating hardware, panel fit, mechanical support and assembled shell/panel isolation must be qualified; plastic-looking housing alone is not proof.
USB shell/chassis and Ethernet shield arrangements remain to be designed without joining the floating output domain. USB data-only still requires valid Type-C attach handling and a verified connection to Teensy's device USB; VUSB–VIN separation must prevent backfeed.
Detection and Bypass Definitions
Table
Function
Confirmed behavior
RMS
Exponential mean-square, time constant 0.5 s Slow or 0.1 s Fast; apply agreed acceleration units/calibration.
Peak
Absolute acceleration over limit for 2 consecutive samples.
Trip latch/reset
Trips latch; reset allowed only after the cause clears. Arming also requires healthy sensor/bias qualification.
Bias fault thresholds
Open ≥20 V, short ≤2 V; adjustable normal window 7–14 V. Faults declared after 5 ms.
Intermittent
Dropouts ≥0.5 ms count as intermittent; exact reference-model implementation/test vectors must be retained during firmware integration.
Overload
98% full scale for3 samples.
Arming
Bias must remain in the normal window 1 s before arming; software checks sensor and sensor cable.
Bypass
Suspends limit and sensor-fault trips only, with unlimited duration. Amber Bypass LED and PC app indicate state. Heartbeat and power supervision can never be bypassed. Processor failure opens the output even in bypass.
Network loss
No protection-state change. Settings changes validated and applied atomically; network processing cannot block acquisition/protection.
2. Decisions, Assumptions and Remaining Questions
Settled Architectural Decisions
Protection remains local to Teensy, independent of PC/network services.
Retain CN0540's DC-coupled DAC offset-cancellation architecture, but recalculate range/scaling and the clock plan; do not copy its analog values unchanged.
Preserve the requested capacitor/rectifier pulse-energy relay drive: static high or low on RELAY_PULSE must not be a steady LED-energy source.
A distinct HEALTH_ACK is issued only after fresh acceleration/bias data and protection processing complete. Missing-pulse cutoff is independent hardware; autonomous PWM cannot establish software health.
Rail supervision and reset provide hard inhibit. Commanded trip/disarm must interrupt LED current directly and actively discharge stored energy, without waiting for health timeout.
Omit informational output readback entirely in revision1. No output-isolated supply is needed for readback.
A single PhotoMOS is not single-fault tolerant: a shorted relay, TVS or output cable can defeat open-circuit shutdown. Stuck-contact detection is outside scope.
Preserve Teensy socketing, 8 MB PSRAM, coin-cell VBAT RTC backup, optional TEDS footprint and external-adapter operation. Coin cell is not protection/recording backup power.
Require durable latest-trip logging/settings, but do not claim that PSRAM-to-flash copy alone solves immediate power failure.
Assumptions Carried Forward
±10 V means vibration amplitude about sensor DC bias, not necessarily a ground-referenced ±10 V DC signal. Validate against the actual sensor compliance and swing.
Trips latch; deliberate rearm is required after valid configuration and cleared causes. Network loss preserves local protection settings/state.
Local DC ground and sensor return share the intended measurement domain; output pair alone floats.
No PoE or mains circuitry; external adapter appropriately isolated.
Four-layer carrier, largely top-side assembly and nominal1.6 mm thickness remain planning starting points, not layout decisions.
Modules, PSRAM/flash, coin cell and panel hardware may be separately installed if assembler policy requires it; policy/budget are pending.
Wrong-BNC survival concerns the intended sensor/controller cables, not arbitrary mains or unlimited-energy sources. Actual maximum sensor-cable voltage/energy remains to be defined.
TEDS is footprint-only revision1 and must not interrupt armed protection. Indicator GPIOs are not individually treated as safety controls.
Open Design/Validation Gates
Table
Gate
Unresolved item and consequence
Review checkpoint
Subsequent explicit shutdown-only authorization superseded planning pause. Shutdown is now wired; stop for user review before other blocks/layout. Qualification remains incomplete.
Shutdown timing
Need a worst-case ≤1 ms bound over10–40°C at actual approximately0.8 mA contact load and chosen LED waveform. Relay's retrieved release limit is at25°C/test conditions, not a full-temperature assembled guarantee.
Health timeout
Approximately10 ms is a provisional candidate, separate from command-release timing; confirm firmware ACK cadence/jitter and allowable hang response.
Output leakage
Show relay + selected TVS + PCB ≤10 µA at10–40°C and actual input voltage, including contamination/production variation. No readback allowance is needed.
TVS coordination
Exact waveform/peak current/source impedance, cable inductance and temperature are unspecified. Candidate maximum clamp limits only support their stated test pulses; no universal surge guarantee.
Connector isolation
Exact insulated rear BNC and hardware stack still require sourced part/import, mechanical review and isolation test; no panel geometry is applied.
Controller
Confirm logic/pull-up tolerances, powered-off behavior, configured shutdown action and controller filtering. Controller/mechanical response is outside ≤1 ms limiter timing.
Sensor
Model, sensitivity, bias/swing, cable length/capacitance and maximum compliance voltage pending.
Analog
Revised ±10 V range, DAC settling/cancellation behavior, overload recovery, noise, numerical whole-chain ±1 dB proof and ADC delay/clock verification remain to be designed.
Recording power failure
Determine whether immediate supply loss must retain pretrigger, whether it is a trip, whether partial posttrigger is acceptable, and what hold-up energy/storage protocol is required. Flash copy alone loses uncommitted PSRAM data and cannot acquire5 s posttrigger without power.
Memory
Verify PSRAM+QSPI flash coexistence on the exact Teensy4.1 revision, supported flash MPN/capacity, write latency/endurance, power-fail-safe atomic commit and nonvolatile settings format.
Assembly/budget
Vendor, consigned-module policy, socket/panel hand assembly, sensor and budget answers pending.
CN0540 Adaptation Evidence and Resolved Conflicts
Range: CN0540 describes 10 V peak-to-peak input with offset up to13 V, not this project's20 V peak-to-peak vibration request. Reference attenuation is0.3 and driver gain2.667. Recalculate gains and all common-mode/headroom/protection limits.
Filter/flatness: sinc5 −3 dB bandwidth is0.204×ODR. At25.6 kS/s this is5.2224 kHz. A calculated ideal sinc5 estimate gives approximately−0.44 dB at2 kHz; this consumes part of the whole-chain ±1 dB budget and is not a complete-chain guarantee. Low-ripple FIR delay is34/ODR, or1.328125 ms here, so FIR is not selected. Sinc5 latency <3/ODR appears in the Typ column;117.1875 µs is planning guidance, not a guaranteed total transport bound.
Clock: CN0540 uses16.384 MHz. ADC ODR is MCLK/(MCLK_DIV×decimation), with power-of-two SPI sinc5 decimation options8–1024. A candidate13.1072 MHz, divide4, decimation128 yields the required actual25.6 kS/s. Independent SPI divider/mode selection is permitted;candidate fMOD3.2768 MHz fits the documented median-mode1.024–4.096 MHz range. Oscillator MPN, jitter, tolerance and full configuration remain unselected.
IEPE headroom: LT3092 dropout1.45 V maximum is documented at10 mA over its specified temperature conditions, not a guaranteed4 mA specification. Nominal26−1.45 =24.55 V leaves0.55 V for tolerances/protection/wiring; connector compliance must be proved or source voltage adjusted.
High-pass conflict resolved: No analog high-pass is selected. Use DC-coupled DAC bias cancellation. The delay requirement concerns converter/filter transport20 Hz–2 kHz, not low-frequency phase/group delay.
3. Electrical and Mechanical Architecture
Diagram
Isolation boundary: only the PhotoMOS optical path crosses from local electronics into the floating contact domain. The TVS and output connector/testpoints stay inside the floating domain. No readback optocoupler or isolated readback supply exists in revision1. No hardware trip latch exists in this block; firmware must latch/rearm, and later reset/upload/all-required-rail hardware must control the default-low release input.
Shutdown Drive — Wired, Not Yet Qualified
RELAY_PULSE transfers energy through coupling capacitor and rectifiers. Static high/low cannot provide continuous relay LED current.
Separate HEALTH_ACK triggers an independent rising-edge retriggerable LTC6993-2; -1 is non-retriggerable and not interchangeable. Candidate hardware timeout approximately10 ms, separate from ≤1 ms command release.
Health, hardware power/reset release and no-trip are combined. A series LED cutoff and active reservoir discharge must assert immediately on trip/disarm/reset/bad power/health timeout.
Actual shutdown boundaries are 5V, 3V3, GND, SHUTDOWN_RELAY_PULSE, SHUTDOWN_HEALTH_ACK, SHUTDOWN_TRIP, SHUTDOWN_RELEASE_N, and power/health status testpoints. These named nets now exist. Later release input must represent MCU reset/upload and all required analog/IEPE rail validity, with default inhibit; it must not be a static GPIO that overrides heartbeat/power supervision. Until later hardware drives release high and trip low, this isolated block defaults inhibited. RELEASE_N is active-low inhibit despite its release-oriented name; R5=1kΩ requires a powered 3.3V release source able to supply approximately3.3mA.
Candidate local TPS3808G01 supervisors monitor5V and3V3. Additional protection-critical rail supervision belongs to the later power block and must feed the hard inhibit explicitly.
TPS3823's0.9–2.5 s watchdog is not the fast missing-pulse gate. Floating WDI may disable it; a1 kΩ ground resistor is recommended to avoid that behavior. It is not placed in this candidate batch.
Fault-inject each RELAY_PULSE and HEALTH_ACK stuck high/low while the other remains active, including bypass. Also test trip/disarm, reset/upload, boot, unpowered, rail ramp/brownout and loss of individual necessary rails. Structural failure-state analysis and partial behavioral pump simulation were performed; no physical fault injection or full-device temperature simulation has been performed.
Schematic Organization and Provisional Teensy Interfaces
All57 objects have exactly one Functional Group: IO U1 Shutdown Contact (54 objects) or IO X1 Floating Output (X1/TP11/TP12,3 objects). Actual inter-block names and testpoint roles are documented in shutdown notes. Wiring uses canonical named-net stubs, not routed PCB copper; schematic legibility/functional subgroup refinement may be reviewed separately. No finalized layout arrangement exists.
Reserved; possible direct trip, but no static permission may override pulse/power supervision.
21
Reserved; output readback omitted.
22
POWER_OK; proposed status only, hardware inhibit independent.
24/25/26/27
LED_ARMED /LED_BYPASS /LED_TRIPPED /LED_FAULT.
Regulated rail
LED_POWER white; indicates rail only, not protection health.
0/1
DEBUG_RX /DEBUG_TX,3.3V UART; no exposed SWD/JTAG claim.
Dedicated Ethernet pads
PHY-specific TX/RX and LEDs; exact orientation essential.
Two module memory pad sites
8MB PSRAM plus supported QSPI flash; exact parts/configuration/accessibility must be verified.
VBAT/GND
3V coin-cell RTC backup, no charging/backfeed.
VIN/GND
Carrier5V with VUSB–VIN link cut; external adapter required even when programming.
All pin assignments remain provisional. Teensy GPIO is not5V tolerant. Never route5V drive/status back to a GPIO without verified translation.
Mechanical Architecture
Hammond extruded-aluminum enclosure candidate with front sensor BNC/five LEDs, rear floating output BNC/RJ45/DC/USB-C, central socketed Teensy/PSRAM/flash and battery, front precision analog zone, separated rear floating-output zone and rear switching-power zone. No enclosure CAD or selected enclosure-fit board outline is applied. An existing default/provisional160×100mm4-layer rectangular board object and unreviewed component positions are present, with132pads/onefill/no routes and bounds extending to y=-155.44mm; these were not altered and are not finished placement.
4. Power, Recording and Parts Direction
Power Tree and Budget Status
External adapter only: 9–24 V input →input protection →5V module/digital rail, plus filtered analog rails and nominal26V IEPE supply. Cut VUSB–VIN link; USB data path must not supply carrier power. Coin cell is RTC backup only. No completed worst-case load/current/thermal budget exists.
CN0540's3.3V-to7V/clean5V/3.3V tree and its28V-to26V IEPE tree are reference architecture, not drop-in converters for this adapter input. Its4.5 mA excitation is changed to4 mA. NominalIEPE delivered power alone is104 mW; losses and every other load are additional. Do not budget carrier loads from the Teensy3.3V output without checking its limit.
LMR36510 candidate accepts4.2–65V and up to1A, establishing nominal input compatibility, not surge immunity or adequate total capacity. Supervisor thresholds/startup ordering/rearm and power-loss recording hold-up remain to be verified.
Durable Recording Requirement and Unsatisfied Power-Failure Case
At25.6 kS/s for10 s there are256,000 frames. Two32-bit quantities/frame would use 2,048,000 payload bytes, before timestamps/metadata/alignment. This is a calculated example, not a selected record format or complete memory budget.
PSRAM is volatile. Copying its pretrigger buffer to flash only after a trip does not preserve that buffer if power disappears before/during the copy, and cannot acquire5 s of posttrigger data while unpowered. The requirement that logs survive power loss therefore needs an agreed hold-up/backup-power or continuous durable-journal strategy, with brownout detection, flash write latency and atomic commit/recovery testing. Whether an immediate power-failure event needs full posttrigger or an explicitly incomplete record remains open. No power-loss logging solution has been built or validated. No microSD is planned.
Candidate Parts and Selection Status
Library availability/stock research is not a reservation or assembler approval. Exact suffixes, approved sourcing and no-unreviewed-substitution rules apply. Shutdown objects below are wired but remain qualification candidates; other blocks remain research only. Generic passives are specified values/packages, not exact qualified procurement MPNs.
Table
Block
Candidate /status
PhotoMOS
AQY212SX U1 wired. Family60V/0.5A absolute maximum, recommended≤48V,2.5Ω max Ron,1µA max leakage,0.2ms max release atIF5mA/ILmax test conditions. Isolation1500Vrms;10–40°C/actual0.8mA release, duration/DC equivalent and assembly isolation not established.
Floating TVS
SMAJ24CA-Q D1 wired across floating output as conditional candidate, NOT accepted as certified protection. PESD30VL1BL exact usable part was not found; its typical-only clamp evidence does not establish guaranteed coordination. D1 remains conditional on leakage/surge/wrong-BNC qualification; details in shutdown notes.
WAGO236-102 X1 internal two-wire interconnect candidate; exact insulated panel BNC still unselected. Amphenol31-5486/31-5540 family investigational; not metal31-5640.
IEPE source
LT3092EST#TRPBF, industrial-grade option if appropriate.4mA resistor setting/compliance pending. LT3494/LT3008 reference boost/LDO candidates not selected supplies.
ADC/reference
AD7768-1BCPZ and ADR4540ARZ-R7 candidates; range/mode/reference loads pending.
Bias DAC/amplifiers
LTC2606CDD#PBF (libraryLTB/lifecycle check required), ADA4807-2ARMZ-R7, ADA4945-1ACPZ-R2 and AD8605ARTZ-REEL candidates; procurement, gain and protection unapproved.
DS2484R+T protocol candidate plus full Class1 current-reversal analog switching/protection footprint. ADG5421FBCPZ-RL7 investigational; ADG5421 withoutF/ADG7421F are not substitutes.
Module/memory
Socketed Teensy4.1/DEV-16996;8MB PSRAM PJRC IC_PSRAM_8MB_SOIC8/APS6404L_3SQR candidate; supported QSPI flash on second pad MPN TBD, no microSD. Module symbols, sockets/heights/pads and memory support unverified.
Ethernet
PJRC-supported LPJ4012AHNL orJ1B1211CCD; exactPHY circuit, pad/interconnect orientation, magnetics and stock pending. Do not guess center-tap wiring.
Power
LMR36510FADDAR, 1 A buck candidate; ADP7118 clean-rail family. Current, dropout, noise and transient budgets remain pending. TPS3823 is only a possible secondary watchdog, not the selected missing-pulse gate.
Locking DC
24V-rated locking jack allowed for9–24V input. Prior rejection based on30V input is superseded. ExactMPN/mating plug, adapter/tolerance/protection coordination remain to be selected; Switchcraft/Kycon24V families may be reconsidered.
PESD30VL1BL research:50nA maximum at30V/25°C, typical34V clamp1A8/20µs, typical42V clamp16A100ns; these are not guaranteed maximum clamp bounds. Complete output leakage now has a confirmed10µA ceiling, while relay alone remains≤1µA.
5. Enclosure and Physical Expectations
Hammond1455N1601 nominal outer160×103×53mm; product page gives maximum PCB159×99mm: manufacturer product page. Provisional rectangle150×99mm front-to-rear is not applied or released. Drawing describes nominal100mm PCB/extrusion length160±0.5mm; reconcile99/100mm width/tolerances and slot thickness before layout. Nominal1.6mm board/fourlayers are assumptions only.
Before layout, verify socket+module+PSRAM+flash height, battery access, end-panel packing, connector protrusions/solder tails, nuts/wrench/plug access, insulation stack, LED/lightpipe solution, USB recovery accessibility, slide-in assembly order, floating-zone isolation and thermal rise. Off-board panel connectors require supported wiring/strain relief; solder tails must not carry panel forces. No board-level isolation certification follows from relay or connector nominal voltage rating.
6. Build Order, Checks and Manufacturing Gates
Current gate: shutdown connectivity built; stop for review and qualification before other subsystems. Remaining staged work:
Table
Stage
Scope /checkpoint
1 Shutdown
PhotoMOS, floating TVS, pulse-energy drive, series cutoff/active dump, health timeout, rail/reset interface, connector and testpoints; no readback. Prove ≤1 ms over 10–40°C, ≤10 µA total leakage, static GPIO faults and default-open states, including bypass.
2 Power
9–24 V locking input/protection, 5 V/clean analog/IEPE supplies, supervision, data-only USB isolation and logging hold-up decision; load, thermal and brownout tests.
3 Sensor/excitation
Insulated front BNC, 4 mA/≥24 V compliance; hot-plug, short, open and wrong-BNC protection for the exact sensor and fault energy.
4 Analog/ADC
DC-coupled DAC cancellation, revised ±10 V scaling, sinc5 at actual 25.6 kS/s; whole-chain ±1 dB over 5 Hz–2 kHz and transport <0.5 ms over 20 Hz–2 kHz.
5 Bias monitor
Per-frame capture; 7–14 V normal window, 2 V/20 V faults, 5 ms declaration, 0.5 ms dropouts and 1 s arming qualification; settling/loading/overvoltage proof.
6 Carrier/firmware/memory
Verified Teensy sockets/pins and reset-safe interfaces; reference-model RMS/peak/overload/latching/bypass; PSRAM plus flash, durable logs/settings, RTC and console.
7 Ethernet
Compatible MagJack; TCP JSON-lines port 50250, one client, no authentication on lab network; no network effect on protection deadlines/state.
8 TEDS
Class 1 current-reversal footprint only in revision 1; defined unpopulated defaults and no disturbance while armed.
9 Integration
Five LEDs, rear USB data port, all testpoints/labels, isolation and fresh ERC.
10 Schematic EE review
Professional approval and resolved electrical, mechanical and procurement gates before layout.
11 Layout, after approval only
Verified outline/stackup/placement/routing; user placement checkpoint, professional EE review, DRC, exports and fit checks before ordering.
Historical pause checks found129floating-pin Errors and6missing-power Errors; actual wiring resolved those. Fresh final ERC reports 4 undriven-net Errors and1 D1 unspecified-pin-type Warning, with no floating-pin, missing-power-connection, driver-conflict or no-connect findings. IC1INA/VDD/GND require laterMCU/power sources; IC1INB is physically driven byQ2collector/R7pullup but the checker does not recognize that transistor/resistor driver. These findings remain explicitly open, not suppressed by fake sources. Read-only net inspection confirms floating outputs contain onlyU1output,D1,X1,TP11/TP12 and never localGND. Partialbehavioral simulations/structuralanalysis are not guaranteed≤1ms release,≤10µA leakage,TVScoordination or physicalisolation proof. No layoutreadiness is asserted.
Manufacturing expectation remains 3–5 prototypes via JLCPCB or PCBWay after assembler, stock, module/panel policies and budget are agreed. Four layers is provisional. Recheck stock at ordering; no similar-name substitution for ADC, driver, reference, current source, fault-protected switches, optical barrier, TVS or MagJack. Write the full bring-up plan and acceptance criteria when a connected reviewed schematic exists. Never attach a ground-referenced scope lead to the floating output.
Firmware-Relevant Hardware Requirements
Fresh acceleration and bias processing completes before HEALTH_ACK; a running timer/ISR is not protection-loop proof. On trip/disarm, disable pulse activity and assert direct hardware inhibit.
Bypass skips limit/sensor-fault trips only, never heartbeat/power/reset protection; indicate bypass in amber and in the app, without a time limit.
Before arming, enforce 1 s of normal bias and sensor-cable qualification. Keep trips latched until the cause clears and a deliberate reset occurs. Retain the reference-model thresholds, time constants and sample counts as acceptance tests.
TCP JSON-lines port 50250, one client, no authentication on the trusted lab network; network loss leaves protection unchanged. Apply configuration atomically and keep nonvolatile settings.
Firmware updates only via rear USB-C; external adapter required, VUSB–VIN link cut and contact open during reset/upload.
Latest trip log: 5 s pretrigger plus 5 s posttrigger acceleration and bias at 25.6 kS/s; PSRAM followed by second-pad QSPI flash, no microSD. Power-failure persistence, partial-record semantics and hold-up remain unsolved design gates, not a completed feature.
Change Notes and Completion Status
Latest attachment fully read and incorporated: no readback; ≤1 ms release over 10–40°C; relay ≤1 µA/total ≤10 µA leakage; unlimited indicated bypass with heartbeat/power unbypassable. Analog flatness, filter, DC coupling, delay, actual ODR and reference-model protection behavior are defined.
Input changed from 9–30 V to 9–24 V with a 12 V adapter; a 24 V-rated locking jack is acceptable. Indoor lab/10–40°C/bench/no ingress and data-only USB/external power/VUSB–VIN cut are confirmed.
TEDS Class 1 current reversal, footprint only; latest trip 5 s +5 s acceleration AND bias, PSRAM then second-pad QSPI flash, no microSD; nonvolatile logs/settings. Immediate power-loss logging remains explicitly unresolved.
TCP JSON-lines port 50250, one client, no authentication on the lab network; USB-only firmware; network loss causes no protection change. Sensor/assembly/budget answers pending.
Earlier authorization led to57disconnected objects beforethepause; no hardwaremutations occurred whilepaused. Subsequentexplicitshutdownauthorization permittedQ1replacement,28namednets,127netstubsegments and5intentionalno-connects. No otherblock/layoutwasbuilt.
Shutdown connectivity/documentation work and limited focused-review fixes are complete for this draft batch; R1 upper-current risk reduced and exact passive candidates annotated without wiring/layout changes. Final-value simulation is behavioral sensitivity, not a guaranteed5mA or10–40°C bound. Guaranteedtiming,currentenvelope,pulse/thermal/capacitorqualification,TVS/leakage,panelBNC andphysicalvalidation remain blocked/open. Exact4ERC Errors/1Warning interpretations and independent findings are in shutdown-focused-review. Overallhardwaredesign,manufacturingreadiness andsafetyvalidation remain incomplete. Power-loss trip logging is a separatelydeferredsystemdecision.
Latest shutdown interface correction — 2026-10-10
Controlling shutdown revision — 2026-10-10
Earlier specification baseline — other subsystem requirements remain in force; shutdown details superseded above
Project Overview and Intended Use
1. What the Device Should Do
Interfaces and Isolation
Detection and Bypass Definitions
2. Decisions, Assumptions and Remaining Questions
Settled Architectural Decisions
Assumptions Carried Forward
Open Design/Validation Gates
CN0540 Adaptation Evidence and Resolved Conflicts
3. Electrical and Mechanical Architecture
Shutdown Drive — Wired, Not Yet Qualified
Schematic Organization and Provisional Teensy Interfaces
Mechanical Architecture
4. Power, Recording and Parts Direction
Power Tree and Budget Status
Durable Recording Requirement and Unsatisfied Power-Failure Case