I couldn’t produce a faithful schematic PDF: the available PDF export covers PCB layers only, and the schematic-rendering fallback loses symbol detail. No PDF was created, and your design is unchanged.
I’ll make a cosmetic-only readability pass using the ten requested blocks, left-to-right signal flow and inter-block net labels. I’ll compare the complete netlist, parts and values before and after, and won’t touch PCB layout.
Thought for 1 min 53 sec
1 day ago
Thought for 7 sec
1/3 Capture baseline component/value inventory and complete netlist invariants
Capture baseline component/value inventory and complete netlist invariants
Arrange ten schematic blocks and clean cosmetic wiring/labels without electrical changes
Compare before/after netlist and visually check readability; stop without PCB layout
Thought for 42 sec
Awaiting 1 task
"Schematic Readability Pass" completed.
Thought for 59 sec
flux
1 day ago
The readability pass is blocked: my available controls do not support schematic canvas placement, frames, or graphical wire/net-label editing, so I made no changes.
Before: 328 components / 188 nets.
After inspection: 328 components / 188 nets.
Parts, values and connectivity remain untouched; no PCB layout started.
I cannot claim the rearrangement or a full before/after netlist comparison was completed. This limitation needs Contact Support.
Final Blocks 8+9 controlling checkpoint — 2026-10-13
Block7 user-approved; final schematic batch built with remaining semantic/physical qualification items below. STOP for user/EE review; no layout/order authorization. This checkpoint supersedes every older CURRENT pause/unbuilt-inlet/TEDS claim below. Inventory328components/188nets; seven additions, no removed components/new nets/group changes.
Completed: R127/R1280805 optional0Ω rework footprints, DNP/DO NOT POPULATE, PCB retained, BOM/P&P excluded. Pad1 IEPE_ENTRY/localGND respectively; both pad2 truthfulNC. No populated TEDS path, GPIO reservation, bridge or Class1 negative-voltage/readout implementation.
Completed logical offboard inlet: J8SwitchcraftL712A CENTER_PIN→DC_INPUT/X2:1/F1, SLEEVE→GND/X2:2, SHUNTNC; selected matching761K plug tip positive/sleeve return. Manufacturer page5A/24V rating; catalogmate evidence https://www.switchcraft.com/dc-power-jack-0-100-2-5mm-pin-solder-lugs-termination-long-bushing/l712a/ ; https://www.marutsu.co.jp/contents/shop/marutsu/datasheet/L712A.pdf . Functional symbol identifiers are NOT maker lug numbers. Librarymissing→createdpart944efc78-5550-47a5-bfc8-8e7d1fe52656,version90b678da-fcba-4e0f-aaa3-af0ff6129814, /xjac0bmichaelx/l712a . ExcludedPCB/P&P, retainedBOM, hand-fit/consigned stockunverified. INSULATE metalbushing fromCHASSIS. Maker drawings blocked in web/computer routes; physical lug map, insulation-stack dimensions and3D unqualified. Verify plug/contact/bushing continuity before wiring; check adapter24V tolerance/transients against jack rating.
Completed constraints only: LED1–5 FRONT BOARD EDGE lightpipe opticalalignment/spacing/height resolve in layout; J5RJ45 REAR panel alignment property. PanelJ1front/J7shutdown+J8DCrear distinct; TeensyownmicroUSBserviceaccess unchanged, NOUSB-C. No positions/outline/routing edited.
Completed source declarations: standardKiCadPWR_FLAG #FLG1PowerOut→5VA(actualU8OUT1), #FLG2→3V3A(U9OUT1), P3→26V_IEPE(U13OUT6). All excludedPCB/BOM/P&P. SENSE/ADJ andSWpins unchanged; no fabricated driver/suppression. FreshERC2026-10-13T00:36:39.511Z 1Error/3Warnings, down9Errors fromfresh10/3baseline.
Failed/blocked terminal semantic cleanup: IC1IN_A onSHUTDOWN_PUMP_INPUT_5V physicallyU6B/R23connected, butU6BUnspecified; repairBi-Directionalmodel. WarningIC1GNDPowerInput/X3:2BiDirectional onGND requiresGround/passiveharness types. D1pins1/2 floatingTVS andD9pins1/2/3GND/TEENSY_3V3/biasclamp lackfunction types; sourcedpassive/polaritymetadata repair required. Current instance mutation tools expose component properties but no terminal override; no blanketcomponentPinTypes set. No actual missing wire identified in this scope, not waived or cleanERC/safety proof.
Requested one-page EE Review Package created in project files: ee-review-package. PopulatedBOM297instances/63groupedtypes; DNP+logicalexclusions separate. FreshsnapshotJ5LCSC5/HQ316,ADC13,BA2032SMLCSC0/DigiKey80065; olderstockfigures below stale. Y1customauthorizedprogramming/consignment andloosecell/strips/761Kassembly accessories remain procurementchecks. Bench/strictshutdownqualification, firmware andrecordingpowerloss remainopen; layout/routing/simulation/independentreview unattempted by instruction.
Ethernet schematic built and user-approved; historical Block7 checkpoint. Final Blocks8+9 checkpoint above controls current status; no layout, routing, firmware or ordering authorization. Inventory atBlock7 321 components /188 nets; added IO J5 Ethernet group, J5/J6/C94.
J5 Cetus/WIZNET J1B1211CCD, PJRC-supported exact part; imported KiCad RJ45_Cetus_J1B1211CCD_Horizontal footprint, maker top-view hole pattern cross-checked. LCSC C910371 lists2548–3091stock in search snapshots, JLCcatalog present; hand-solder/consign and recheck before purchase. Imported STEP URL failed: 3D model/MCAD fit remains unattempted. No similar-MPN substitution.
Actual module signals use U31 named T+,T−,R+,R−,LED,GND; module-library arbitrary pin numbers are NOT physical connector numbers. PJRC card11b graphic pad order as printed: RX+ | RX−; LED | GND; TX− | TX+. Carrier J6 2x3/2mm own numbered map 1TX+,2TX−,3GND,4LED,5RX−,6RX+. Harness connects by SIGNAL to module pads, not through J2/J3; top/bottom views must not be confused or assumed numerically straight-through.
Netmap: ETH_TX_P U31T+→J6/1→J5/1; ETH_TX_N T−→J6/2→J5/3; ETH_RX_P R+→J6/6→J5/4; ETH_RX_N R−→J6/5→J5/6. J5/2+5→ETH_PHY_CT→C94=100nF/25V/X7R0805→localGND, exactly PJRC CT topology, NEVER3V3. Green 10anode→U31LED/J6/4,9cathode→GND; current limiting is 150Ω already on Teensy R3, not GPIO or new rail. Yellow11/12 andNC7 unused. Typical green current order5–10mA; verify on bench; front LED values/reservation unchanged.
Isolation choice differs deliberately from PJRC local-ground shell: J5/8 cable-side internal1nF BobSmith return and both metal shell pads13/13_2→CHASSIS ONLY. Integrated four75Ω cable-side terminations are not PHY CTs. No extra external shield/local coupling or earth lead; R49/C68 10MΩ||1nF remains the only intentional CHASSIS–localGND network. Shielded network cable can earth CHASSIS, not directly sensorGND; no shutdown conductor joins these nets. Cetus does not specify internal capacitor voltage rating in its drawing; assembled isolation verify on bench.
Assembly: generic2mm carrier header J6 from PJRC/SparkFun kit, additional hand-fit2mm module header and short ribbon (PJRC OSH reference89361-706LF sockets/120mm ribbon); these off-module accessories are assembly consumables, not fictional carrier pads. J5/J6 excludedP&P, retainedPCB/BOM. Required rear MagJack alignment and Teensy microUSB clearance remain constraints only, no physical placement claimed. Use signal-labelled harness continuity checks before power.
Load assumption: reserve 100mA at TeensyVIN/5V for Ethernet-enabled PHY+greenLED/activity, within existing1000mA digital5V envelope, not added carrier3V3 load; verify on bench. NoPoE; no added custom ESD circuit beyond proven reference magnetics/termination.
Bench acceptance additions: unpowered six-wire signal/polarity continuity; shell/CHASSIS vsGND10M path and isolated shutdown conductors; 10/100 link and packet transfer under acquisition; network disconnect never changes shutdown permissions; measure Ethernet-on rail current/greenLED and shielded-cable ground-loop behavior. No empirical/safety qualification claimed.
Fresh scoped net readback confirms all six signal/CT nets and CHASSIS membership; ERC 2026-10-12T23:44:36.400Z remains10Errors/3Warnings, delta0/0, no new Block7 finding. Baseline power-model/IC1/diode issues not suppressed. Circuit/stock/reference documentation completed; physical harness orientation qualification, 3D model and bench acceptance outstanding, not overall completion.
Block 4 and Block 5 are user-approved. The small approved Block 5 LED/programming-access adjustments below are implemented; STOP before Ethernet (Block 7). This section supersedes older Block 4 pause/status, carrier-supply and partial-checkpoint statements throughout this file. No layout/order or overall project-completion approval is implied. Inventory unchanged: 318 components / 182 nets.
Completed: C85 bias reservoir and authorized pre-programmed Y1 procurement notes; U31 schematic-only socketed module, J2/J3 carrier sockets; complete GPIO interface wiring; U32–35 dual-rail translators with local decoupling and defined enable/source/receiver biases; independent shutdown command polarity and original healthy AND chain retained; U30/C78/D9/R82/R83 moved to actual TEENSY_3V3, never tied to independent carrier3V3.
Completed: five separately driven status LEDs, BT1 VBAT holder connection (no charger), J4 buffered UART, and U36/U37 on-module memory accessories with U38 split logical pad representation. U31/U36/U37 are excluded carrier PCB/P&P; U38 is also excluded BOM. J2/J3 procurement MPN corrected to SSQ-124-02-G-S; imported standard footprint remains physically unqualified. Bare module requires hand-fit two24-pin male strips; VBAT uses an underside-pad wire, not the main48socket contacts. Loose CR2032 and male strips are assembly consumables, not independently placed carrier copper.
Implemented GPIO allocation: 0RX/1TX UART;2pulse/3ACK/4release/5trip;6DRDY;7reset/8sync/9START;10ADC-CS/11MOSI/12MISO/13SCLK;14bias/15input-fault/16bias-output-fault;17POWER_OK/18digital5V/19carrier3V3/20analog5V/21analog3V3/22IEPE healthy;23DAC-CS;24Armed/25Bypass/26Tripped/27Fault;28clock-status/29AFE-OE_N/30shutdown-OE_N;31–41 reserved. Exact implementation is the current netlist, not the older candidate map.
Implemented translator map: U32 Teensy→analog controls plus UART TX; U33 Teensy→carrier shutdown commands; U34 carrier→Teensy healthy monitors/UART RX; U35 analog→Teensy MISO/DRDY/clock. U32/U33 OE have10k pullups toTEENSY_3V3. GPIO must initialize safe levels before bank enable; ACK must follow fresh completed protection processing, never a free-running timer. J4 pins1GND/2TX/3RX, no power pin; TX throughU32 is unavailable until AFE bank enables, so it is not an early-boot console.
Memory source correction: official PJRC cores7f107ee0a309 startup.c435–442 and core_pins.h1056–1062 identify GPIO48RAM-CS,49DATA1,50DATA2,51FLASH-CS,52DATA0,53CLK,54DATA3; U38 connects those actual on-module logical pads. U36 PSRAM and U37 W25Q128JVSIM TR have separate chip-selects/shared bus, not carrier expansion headers. Official LittleFS8c2badab74a0 lists the JV-M family. Sources: https://github.com/PaulStoffregen/cores/tree/7f107ee0a309/teensy4 and https://github.com/PaulStoffregen/LittleFS/tree/8c2badab74a0 . Accessory operation/coexistence is untested; no power-loss recording guarantee.
Failed/unresolved qualification items: boot/reset/upload/stuck-pin and intermediate-rail safety behavior has not been qualified; shutdown acceptance remains strict. Verify inhibition until valid rails, clock, settled calibrated frames and bias, fresh ACK timeout and each missing rail on bench. Socket drill/mating/height, module male strips/VBAT wire assembly, memory package fit, loose coin-cell procurement and complete powered-USB separation procedure remain assembly/release gates. No claim that generic footprint is manufacturer-qualified or that supply pin types in the module library are corrected. Component limit facts whose original citations are not retained in this checkpoint remain subject to the sourced tool evidence and EE review, not an uncited qualification claim.
Load reservations (engineering assumptions, not measured): allow50mA externalTEENSY_3V3 carrier load plus80mA memory-accessory allowance; allow30mA all-five LED normal-operation reservation at5V plus20mA translator/digital activity overhead within existing1000mA5V budget. LED nominal sum25.36mA; reserve an additional1mA module GPIO base-drive load. This is not a guaranteed maximum; measure actual currents before release.
Outside Block5 batch: firmware implementation, TEDS effort, layout/MCAD/manufacturing, power-loss hold-up/durability solution and module-library repair. Ethernet special-pad wiring is now built under controlling Block7 checkpoint above; USB host/D+/D− remain unused, programming uses own microUSB.
Verification completed: read-only net inspection confirmed separate32-pinTEENSY_3V3, OE pullups, trip/release defaults, independent RAM/flashCS and bufferedTX; summary confirmed318/182. Fresh ERC 2026-10-12T22:32:59.095Z:10Errors/3Warnings, versus12/3 baseline:−2Errors,0Warnings. Prior DRDY/MISO single-pin errors resolved; no newly introduced floating pin/driver conflict/short reported. Remaining baseline missing-power/IC1 undriven and diode pin-semantic reports are not suppressed; not clean ERC or safety qualification.
Approved Block 5 small adjustments — 2026-10-12
All five front lightpipe LEDs now target approximately5mA on existing5V, without wiring or driver changes. White LED1 is directly resistor-fed; the other four retain MMBT3904LT1G low-side drivers,10k base resistors and100k base-emitter pulldowns (~0.25mA/GPIO). Assume VCE=0.10V for nominal selection; the exact5mA/0.25mA operating point is not specified in the transistor datasheet, so verify VCE and brightness/current on bench, not a corner-temperature proof. Datasheet curves are only reference conditions.
Selection uses I=(5V−VF−VCE)/R (VCE=0 for white). Resistors retain0603 footprints, now1%/0.1W; normal estimated dissipation10–17mW. Amber manufacturer recommends above5mA for best long-term performance;560Ω gives a nominal estimate above5mA, not a guaranteed bound.
Practical procurement metadata set on actual resistors: R88 FOJAN FRQ0603F3900TS/C5204056; R89/R91 FOJAN FRC0603F6200TS/C2907058; R90/R92 YAGEO RC0603FR-07560RL/C114629. LCSC search snapshots respectively60,600/109,200/14,800 stock; not reserved, recheck before assembly. Actual LED Current/Current Rating/Role Details and driver notes updated.
Programming uses only Teensy's own microUSB after rear end panel removal. Cut VUSB–VIN pad before first use, disconnect sensor before attaching USB, and remove USB before reconnecting sensor; cutting the pad does not isolate USB ground. U31/J2/J3 properties explicitly require provisional module USB end toward rear and plug insertion/removal, cable body/bend and finger access with panel removed. No panel datum is sourced; clearance/orientation is a requirement for layout/MCAD, not implemented placement or validated fit. No carrier USB connector is authorized or built; no PCB positions/outline changed. Ethernet is next scope, unattempted here.
Scoped read-only verification: actual resistor values/LED current metadata and U31/J2/J3 access constraints read back; LED wiring unchanged. Fresh ERC2026-10-12T23:25:31.001Z remains 10Errors/3Warnings, delta 0/0 versus pre-edit2026-10-12T23:22:33.677Z; no new findings. Items1–3 completed; no failed edits. Ethernet/layout/MCAD and empirical LED/fit qualification unattempted. STOP here.
Block 4 is user-approved; Block 5 is authorized but NOT built or complete. Stop remains required after Block 5; no subsequent block is authorized here. Inventory after the two scoped additions: 250 components / 117 nets.
Completed electrical addition: C85 Murata GRM1885C1H102JA01D, 1nF/50V C0G, MCU_IEPE_BIAS_0V28 (after R87=22kΩ) to local GND. Place at actual Teensy ADC pin when carrier integration is built; actual pin connection/placement remains unattempted. Nominal R87×C85=22µs, 5τ=110µs; additional source impedance and ADC acquisition/dropout response for 0.5ms interruptions verify on bench. LCSC lookup snapshot98,380 pieces, not reserved.
Completed BOM instruction: Y1 retained unchanged electrically, OE HIGH on3V3A; actual Role Details now requires AUTHORIZED distributor factory/distributor-pre-programmed13.107200MHz, hand-fit or consigned. Exclude from Pick & Place=true; Allow Substitutes=No. No stock/order/quote claim.
Unattempted build items: Teensy/socket/header realization; complete ADC/DAC/bias/fault/shutdown/rail-monitor pinmap and wiring; partial-power buffers and U30/C78/D9/flag pullup supply migration; five LEDs/drivers; PSRAM and second-pad QSPI flash; VBAT coin-cell holder; UART debug header; physical Ethernet/USB access reservations. Preliminary sourcing only, not completion.
Library-module sourcing gap: 48-terminal Teensy4.1 part3e1c3c52 omits VBAT and special/internal connections; 65-terminal part68d4b306 has suspect nonphysical numbering (e.g. D− pin number D), lacks memory expansion representation and has inappropriate supply pin types. Neither was instantiated; corrected/imported module and verified socket land patterns remain unresolved engineering work, not a user-specification blocker.
Controlling power correction: carrier3V3 is independent LT1763 output; Teensy must use existing5V atVIN and its own separate TEENSY_3V3 output. Never tie regulators or feed Teensy3V3 without PJRC-supported modification. U30 still physically uses carrier3V3 in this partial checkpoint; it is NOT yet tied to actual MCU supply. Earlier same-domain/future-3V3-feed statements below are superseded; migration must occur in carrier integration before operation.
Official reference: https://www.pjrc.com/store/teensy41.html — VIN supplied5V, separate VUSB–VIN link before externally powered USB use, onboard3V3 external load recommendation250mA,3V CR2032 VBAT reference, PSRAM on smaller underside footprint and flash on larger. No fictional reset pin: PJRC states Teensy4.1 has no exposed hardware reset signal. Actual carrier reset/upload inhibit implementation remains unattempted.
Scoped verification completed: fresh ERC2026-10-12T22:10:23.939Z remains12Errors/3Warnings, delta0/0 vs supplied baseline; C85 floating pins resolved and direct net readback confirms reservoir and unchanged Y1→R86→ADC clock. No approved shutdown/isolation wiring changed; no broad review, simulation, layout or next-block build.
Rev1 laboratory acceptance policy — 2026-10-12
User-approved basis: Rev1 LAB prototype uses typical datasheet values, sensible margin and manufacturer reference topologies; performance is first-board bench acceptance, not production/full-temperature/tolerance qualification. Missing guaranteed performance is marked verify on bench, not a reason to stop safe progress. Absolute maximum pin limits still apply. Shutdown safety and shutdown-BNC isolation remain strict and unchanged.
Block 3 approved and Block 4 controlling revision — 2026-10-12
Block 3 is user-approved. Pre-Block-4 hardware inventory: 180 components / 73 nets. U23 LT3092 source is 4.010 mA nominal; D7 TVS2700 primary clamp, D8 SET/OUT limiter, C60 470 pF compensation, R40/R48 330 Ω independent DC branches, and TP20–25 are built/wired. IEPE_PROTECTED_INPUT and IEPE_PROTECTED_BIAS remain HIGH-VOLTAGE interfaces, not MCU-safe: design for −5..35 V primary transient screen plus overshoot. J1 Amphenol RF 031-10 insulated front BNC is off-board/excluded PCB and P&P, shell local GND; X3 is its internal harness. Panel drawing/stack and assembled insulation remain qualification gates.
Revised IEPE rail: 26.3284 V nominal, 25.7159–26.9449 V static corners; 24.0259 V allocated minimum connector compliance, 26.9649 V maximum open-circuit voltage. User accepts 1.45 V dropout as an engineering allowance, not a guaranteed 4 mA datasheet limit. R28=169 kΩ; R30=422 kΩ in series with R50=6.81 kΩ; boost=28.64 V nominal. Compliance is no longer blocked by the obsolete unmodified-rail calculation. First-board acceptance: connector compliance ≥24 V and open-circuit ≤28 V. Mandatory bench test: TVS2700 leakage at 26.97 V open-circuit, including temperature/loading consequences. No measured compliance, leakage, stability or EMC claim.
Compatible sensor bias/swing/sink and cable capacitance must still be qualified; ±10 V is not possible for every 7–14 V bias sensor. 30 m cable is limited by a tested capacitance envelope; earlier 3 nF and 3 mA sensor reservation are provisional engineering assumptions. Grounded-housing sensor return is the sole intended low-impedance external ground.
Current workflow: one block at a time; stop after Block 4 for user review. Earlier waived intermediate pauses are no longer controlling. Do not build the carrier, firmware, Ethernet or subsequent blocks in this batch.
Grounding and sensor requirements — 2026-10-12
This section overrides earlier unknown sensor/cable and grounding assumptions, without authorizing a completed-input or isolation claim. Support compatible IEPE accelerometers with grounded housing/signal return. Use fixed 4 mA excitation with an accessible, resistor-swappable setting and rework space, not software adjustment. Maximum cable length is 30 m; broad coax compatibility is limited by a tested total-capacitance envelope whose numerical limit is still to be determined.
During measurement, sensor return is LOCAL_GND and the only intended low-impedance external ground connection. Require an isolated-output adapter with no secondary earth bond; transformer-isolated Ethernet with no cable-shield earth bypass; isolated shutdown output; and no direct enclosure/local-ground/earth bond. Metal chassis is a separate domain. User-approved and populated chassis coupling is 10 MΩ in parallel with 1 nF (R49/C68); EMC qualification remains required and this does not eliminate all AC loop current.
USB programming ALWAYS requires sensor disconnected; remove USB BEFORE reconnecting sensor. Shaker-off alone is insufficient; no USB isolator is required for this accepted workflow. Never lift USB ground while retaining D+/D−; cutting VUSB–VIN does not isolate USB ground. Tested ground-offset rating is NOT established; ±30 V DC and IEC 61000-4-2 ±8 kV contact/±15 kV air remain first-board validation targets. Sensor return is local ground, not a rated differential common-mode input. Exact adapter, magnetics, shielding, insulation and ESD paths require assembled qualification. Full limits: grounding-and-esd-plan.
1. Status and authority
Current consolidated specification,2026-10-12. Schematic in progress, not approved for layout/order. Block 3 approved; Block 4 requires a user-review stop. Professional EE review of the complete schematic before layout and of layout before ordering remains required. specification-revision-history is historical evidence, not current inventory, topology or approval state.
Controlling implementation records: shutdown-design-notes, shutdown-focused-review, power-budget, power-design-notes, iepe-input-design-notes, with the current rail/bandwidth/workflow revision above controlling. Pre-Block-4 schematic 180 components / 73 nets. Shutdown, protected entry, digital/analog/IEPE generation, five rail detectors and Block 3 source/protection are built. Startup/missing-rail/partial-power, inlet mapping, fault-energy/thermal/Ceff and carrier reset/upload remain qualification gates. No approved layout/order, measured safety certification or power-failure logging solution.
2. Intended use and environment
Standalone single-channel IEPE vibration limiter for an m+p VibRunner-controlled shaker. Protection is local, independent of PC/network. Indoor laboratory,10–40°C,bench mounted,no ingress rating. Initial3–5prototypes; not a certified SIL/PL/personnel-protection controller. Sensor model/cable,assembly policy and budget remain pending. External isolated adapter; no mains or PoE.
3. Shutdown requirements and actual revision
Normally-open PhotoMOS permission contact closes only when powered,armed,healthy and dynamically driven. Loss of DC,necessary rails,reset/software progress or either safety pulse stuck HIGH/LOW must remove permission. Hardware command-to-contact-open ≤1ms excludes hang detection,controller filtering and mechanical stop; room/40°C bench acceptance is required, no measured result claimed. Retriggerable rising-edge LTC6993-2 timeout 9.91232ms nominal, separate from command latency.
Actual drive: TC4427A channelA, capacitive pulse-energy coupling/rectification,reservoir, direct Q3 series LED cutoff, independent health qualification, digital rail supervision. No active discharge/dump circuit is required or installed in the controlling revision. Firmware must stop RELAY_PULSE on trip/disarm/not-ready; continuous PWM while inhibited is a required fault test. No hardware trip latch; firmware latches/rearms. RELAY_PULSE and HEALTH_ACK are pulse-required; valid DC TRIPLOW/RELEASE_NHIGH permissions cannot alone energize without pulses and valid power.
R1=180Ω,R9=22Ω,R11=10kΩ,C1/C8=1µF; RELAY_PULSE40kHz50%duty. LED minimum acceptance 4.5mA =1.5×3mA manufacturer maximum turn-on criterion; this is separate from5mA release-test conditions, not a guaranteed40°C timing proof.
SHUTDOWN_RELEASE_N defaults inhibited through R5=2.2kΩ and now joins ONLY R5/U5MR, never fixedHIGH. One70kΩminimum internalpullup gives defaultlow≤0.03077VDD withR5max2222Ω. High-source allowance≤1.552mA at3.380V/R5min2178Ω excluding leakage. U4/U10/U11 MR tied their own monitored supplies, not RELEASE. U21/U22 AND all FIVE healthy outputs; final POWER_OK has10k pulldown. Four TPS3808 CT-open delays12–28ms, U15 finalHV release delay10.64–21.844ms with5.6nF±5% assumption. MRLOW≤0.3VDD/HIGH≥0.7VDD; MCU release/reset/upload integration still pending.
U6 SN74LVC1T45 dual-supply translator,VCCA3V3/VCCB5V/DIR3V3; R23=10kΩpulldown,C10/C11=100nF. SHUTDOWN_RELAY_PULSE is the3V3 boundary; U6B→SHUTDOWN_PUMP_INPUT_5V→IC1IN_A. Manufacturer Ioff/either-supply-atGND high-Z supports missing-rail interface; intermediate ramps still need bench testing.
Output readback omitted revision1: no CONTACT_SENSE,second optocoupler,output-isolated supply or stuck-contact proof test. Single PhotoMOS/TVS/cable are not single-fault tolerant.
4. Interfaces and isolation
Front: insulated sensor BNC plus whitePower,greenArmed,amberBypass,redTripped,amberFault lightpipe LEDs at approximately5mA each; no buttons. Rear: insulated shutdown BNC,compatible MagJack,locking DC inlet. Programming accesses Teensy's own microUSB with rear end panel removed; no additional carrier USB connector.
Shutdown BNC center=VibRunner terminal8;shell=floating controller digitalI/Oground. Never join either floating conductor to local GND,sensor return,chassis,USB,RJ45 shield or mounting hardware. User measured3.28Vopen,approximately4.1kΩpullup/0.8mAclosed; these are nominal measurements,not guaranteed limits. Reported1nF/2kVcontroller-ground/chassis coupling is not system isolation certification.
Relay requirements: Ron≤5Ω,relay-alone offleakage≤1µA,rating≥40V/100mA,input-output isolation≥1.5kV. Complete output relay+TVS+PCB leakage ≤10µA at room temperature by bench acceptance; no analytical10–40°C guarantee. Existing SMAJ24CA-Q across floating pair accepted for prototype,not arbitrary surge/single-fault certification. At nominalpullup the10µA limit gives41mVdrop;5Ωclosedcontact gives≈4mV. Controller thresholds/powered-off behavior remain to confirm.
X1 WAGO is internal harness to selectedrearJ7Amphenol031-10 insulatedpanelBNC. Insulating hardware,strain relief,panelfit and assembledshell isolation remain open. TP11/TP12 require isolated probes only; never ordinary grounded oscilloscope ground on either conductor. TP9/TP10 measure LED current by measuredR1; account for probe loading in leakage tests.
5. Sensor,analog and acquisition requirements
IEPE source built: 4.010 mA nominal, ≥24 V connector compliance target. Digital5V→TPS2553-limited LT8330/external diode 28.64 V nominal boost→LT3008 26.3284 V nominal clean rail→LT3092. Revised corner/allocation and first-board acceptance are stated above. LT3092 1.45 V allowance is user-accepted engineering screening, not a guaranteed 4 mA limit.
CN0540-derived DC-coupled DAC bias cancellation,AD7768-1,requested±10Vvibration about sensorDCbias; no analog high-pass. CN0540 reference10Vpp is not20Vpp; recalculate gain/headroom/commonmode/protection.
Analog chain flatness ±1 dB from 5 Hz to 5 kHz; do not reduce this requirement to 2 kHz. Firmware-selectable detection bandwidth: 2 kHz default or 5 kHz.
AD7768-1 ODR 51.2 kS/s, sinc5 low-latency. Expected/candidate sinc5 droop around −0.7 dB at 5 kHz, not measured and not a full-chain acceptance result. Firmware applies selected 2/5 kHz band filter then anti-aliased decimation; detection AND trip recording run at 25.6 kS/s. Firmware implementation is a future block.
Analog + converter delay <0.5 ms over the revised bandwidth; excludes detection/RMS windows but does not waive5kHz. Selected 13.1072MHz MCLK /4,median mode,sinc5 decimation×64,fMOD=3.2768MHz; valid divider/power/register settings verified anddocumented below,firmware application future. Y1 physical programmable source is built; customprogramming procurement andjitter/completechain timing requirebench acceptance. Typical sinc5<3/ODR gives<58.6µs at51.2kS/s,not a guaranteed complete-chain bound.
High-impedance bias divider/buffer→TeensyADC once per vibrationframe,normal0–28Vmeasurement; installed output MCU_IEPE_BIAS_0V28 represents approximately0–2.77V. Protect for actual open-circuit excitation/agreedwrong-cableenergy. Sensor sensitivity,bias/swing,cablecapacitance and maximumvoltage pending; no arbitrary mains fault survival.
TEDS IEEE1451.4 Class1 mixedmode/current reversal,footprint only revision1; generic1-Wirebridge alone is not complete interface. Must not disturb armed protection.
Bypass suspends limit and sensor-fault trips only,unlimitedduration,amberLED/PCindication. Never bypass heartbeat,power or reset supervision. HEALTH_ACK onlyafterfresh acceleration+bias+protection complete; autonomousPWM/timerISR is not healthproof. StopRELAY_PULSE and assert directinhibit ontrip/disarm. Networkloss never changesprotectionstate; network processing cannotblockacquisition.
Programming through Teensy's own microUSB only, after removing rear end panel; externaladapter required for carrier operation. Cut Teensy VUSB–VIN pad before first use. Disconnect sensor before USB; remove USB before reconnecting sensor. Use device, not USB host. No carrier USB connector/CC/ESD circuit build is authorized. Outputopen duringreset/upload. CoincellRTCbackup only,nocharge/backfeed orrecordingbackup.
8. Carrier,memory,network and recording
SocketedTeensy4.1; exactsocket/pads/heights/pinmapping unverified. GPIO not5Vtolerant. Provisionalinterface map and candidateparts are preserved in historicalspecification for research, not authorityto wire; verifyexactmoduleandperipheralpinouts.8MBPSRAM+supportedQSPIflashsecondmemorypad,flashMPN/coexistence/endurance/writelatency pending; no microSD. Debug3V3UARTconsole; no SWD/JTAGclaim.
EthernetTCPJSON-linesport 50250,oneclient,noauthenticationontrustedlabnetwork; USB-onlyfirmwareupdate. Actual Block7 J1B1211CCD circuit, source-verified PHY named pads/CTs and CHASSIS-only shell termination are built as recorded above; firmware and bench qualification remain future work.
9. Mechanical,assembly and release gates
Hammond1455N1601candidate:manufacturermaxPCB159×99mm; proposed150×99mm rectangle notapplied/released. Reconcilemanufacturer99/100mmwidthanddrawingtolerances/slots. Socket/module/memoryheight,batteryaccess,panelpacking,plug/nut/wrenchaccess,insulation,strainrelief,slide-inassembly andthermalfit needreview. Fourlayers/nominal1.6mm/largelytop-side areplanningassumptions; existingprovisional/default160×100mmboard/unreviewedpositions are notapprovedoutline/placement. NoMCADbuild. Provisional required module orientation: Teensy microUSB end toward rear. With rear end panel removed, layout/MCAD must reserve and verify actual USB plug/cable insertion, removal, body/bend and hand access. U31/J2/J3 carry this constraint; no arbitrary socket movement or board-outline edit and no implemented panel-clearance claim.
Manufacturing3–5prototypes viaJLCPCB/PCBWayaftervendor/consignment/handassembly/budgetagreement. No manufacturingprofile/export/order changes inthisbatch. Recheckstock; no unreviewedsimilarname substitutions forprecision/safety/interfaceparts.
Remaining sequence: Block 4 analog/ADC/bias → STOP for user review → carrier/firmware/memory → Ethernet → TEDS footprint → integration → professional EE review → layout only after approval → layout EE review/DRC/export fit → order. Current one-block-at-a-time user pauses control; earlier waived pauses do not. No simulation is requested in this bounded Block 4 batch; EE and bench gates remain.
Specification correction was completed and full-read BEFORE initial schematic changes. Initial37 plus follow-up32 = 69 Block4 components, one existing group ANALOG U24 Precision Acquisition; current inventory 249 components / 117 nets / 15 groups. No approved shutdown/isolation/source redesign; no carrier, firmware, layout or TEDS build. Only added Block4 loads use existing rails.
Table
Assigned item
Status and actual implementation
Specification update first
Completed: stale ADC-rate/flatness/compliance/Block3 and pause statements replaced, accepted rail/dropout/leakage tests recorded.
Completed: U26 DAC80501MDGSR,5VA,internal2.5V reference,220nF VREFIO,SPI2C=GND; AFE_DAC_RAW now connects throughR81 toU29C subtraction amplifier. POR midscale/gain2 implies nominal2.5V; internal reference enabled. Startup is NOT calibrated cancellation or an arming permission.
FDA/ADC drive
Completed schematic portion: U27 THP210DR,5VA/GND,PD tied high (enabled),VOCM from ADC_VCM_2V5; R58/R59=1k,R60/R61=2.4k crossed negative-feedback arms; R62/R63=33Ω,C75=4.7nF differential reservoir. PD high enables operation.
HV front end and cancellation
Completed schematic: U28 ADG7421FBCPZ-RL7, U29 OPA4192IDR. Separate three300k/100k dividers BEFORE protected switch sources; U29A signal follower,U29B VCM follower,U29C gain1.5 difference,U29D bias follower; DAC output already buffered internally. Installed matched10k/15k network with220pF across15k arms; no analog high-pass.
Bias monitor
Completed schematic: U28 second protected divider channel→U29D→U30 ADG7421FBCPZ-RL7 powered by carrier3V3→R87=22k→D9 BAT54S-TP rail clamp→MCU_IEPE_BIAS_0V28. U30 follows MCU supply, not independent3V3A, to prevent powering an absent receiver. Unused U30 channel grounded/disabled,D2NC. Future carrier must power Teensy from this same3V3 domain and verify ADC acquisition with22k source resistance.
Physical clock
Completed schematic: Y1 SG-8018CG 13.107200 MHZ TJHPA,3V3A,OE high,C84=100nF,R86=33ohm series→ADC_MCLK_13M1072. Factory/distributor-programmed oscillator, not firmware-programmed. Exact configuration is the procurement instruction; use Epson/authorized programmable-oscillator service, not broker inventory or an alternate frequency. No stock reservation/order claimed; custom-programming quote and jitter/noise acceptance remain procurement/bench gates, not a missing schematic source.
Scoped verification
Completed direct connectivity read and fresh ERC delta below; no floating pins/shorts/driver conflicts introduced. Bench performance and professional review remain open. No simulation, PCB placement or manufacturing readiness claim.
Firmware interfaces/configuration: SPI_AFE_SCLK/MOSI/MISO, SPI_CS_ADC_N, SPI_CS_DAC_N, ADC_DRDY_N, ADC_RESET_N, ADC_SYNC_IN_N, ADC_START. Derived bit-packed values: 0x15=0x22 (CMOS CLOCK_SEL00,MCLK_DIV10,median PWRMODE10,powered on,raw modulator off); 0x19=0x01 (sinc5 Filter000,DEC_RATE001=×64). fMOD13.1072MHz/4=3.2768MHz lies in sourced median recommendation1.024–4.096MHz; ODR=fMOD/64=51.2kS/s. These are documented future firmware writes, not programmed hardware.
Reference buffer requirement: 0x16=0xA0, full REF+/REF− buffers, analog-input precharge retained (derived code10 in fields[7:6]/[5:4]). Full buffer reference limits includeAVSS..AVDD1;4.096V/GND on5V meets them.
R51=10k pulls ADC_RESET_N low; R52/R57 pull CS high. R53–56 pull GPIO0–2/START low. R64 holds SYNC_IN_N high; R65–67 pull MCLK/SCLK/MOSI low. R68=100k now weakly biases AFE_LEVELSHIFT_OUT to AFE_VCM_BUFFER; R59 FDA return also uses this follower, leaving ADC VCM lightly loaded. Future carrier must release reset, write/read back ADC/reference registers, verify/synchronize clock, measure bias, set DAC approximately0.0991×sensorDCbias, calibrate offset and wait for fresh settled frames. Keep shutdown inhibited until calibration, valid bias and rail/clock health; inhibit on clipping or either fault flag. Increasing DAC lowers acceleration output; increasing sensor input raises ADC differentialAIN+−AIN−. DAC POR2.5V can clip many normal biases: no guaranteed±10V range before configuration.
Installed front end/protection: R69–71 andR72–74 each total900k; R75/R76=100k; R77/R78=10M protected-drain bleeds. Each normal input loads sensor approximately1M; combined draw≈56µA at28V. Unloaded divider0.1 becomes≈0.099075 including10M bleed andexisting330ohm branch; calibration accounts for this. U28 sources see0..2.8V normal and−0.5..3.5V primary screen, not directHV. Source faults disconnect regardless of enable; typical threshold is0.1V outside supply rails and drain initially follows during fault response. Power-off channels remain open with−60..60V at sources. The900k impedance limits possible primary-screen clamp injection to tens ofµA; switch protection plus bleeds addresses absent5VA. This is a credible lab topology, not arbitrary-energy/zero-leakage certification: verify rail lift, drain peaks, partial-power and shutdown inhibition on bench.
U30 supply/enable andR82/R83 flag pullups usecarrier3V3. R79=100k discharges its output when open. D9 pin1=GND(anode),pin2=3V3(cathode),pin3=MCU analog junction, pinout verified. R87=22k limits even5V drain excursion to<0.1mA at3.3V rail; BAT54S maximumVF240mV at0.1mA/25°C supports nominal receiver clamp margin. Normal bias output≈0..2.774V; bench-check leakage/offset, acquisition time and missingcarrier3V3 behavior. Negative input fault may discharge slowly through10M/parasitics but firmware must treat invalid bias/flag as inhibit, not acceleration data.
Bounded DC/headroom calculations, not measurements: U29C output=VCM+1.5×(buffereddivider−DAC); installed overall≈0.35667 afterFDA2.4. Calibrated±10V→±3.567V differential with≈0.529V reference margin; outputs≈0.717..4.283V at2.5VCM. FDA summing CM≈1.976..3.024V fits sourced1..4V on5V;100mV output headroom is typical. U29 rail-to-rail inputCM−0.1..5.1V on5V supports0..2.8V follower input andapproximately1..2.665V difference inputCM. Sensor itself must sustain requested bias±10V within0..28V; no promise for every7–14V sensor.
Filter and delay: C82/C83=22pF divider shunts; C79/C80=220pF matched acrossR84/R85=15k gives48.2kHz difference-stage pole; existing33+33ohm/4.7nF ADC reservoir gives513kHz pole. Switch source/drain on capacitance13pF each is typical. Assumption: additional opamp/layout capacitance allocated20pF, giving68pF total at≈89.2kThevenin; verify on bench. Derived dividerτ≈6.07µs/fc26.2kHz; combined ideal analog droop≈0.20dB at5kHz, essentially DC-flat at5Hz. Expected sinc5≈0.684dB is additional converter droop; estimated combined≈0.89dB, not measured. Estimated analog delay≈10µs plus5µs amplifier allowance andtypicalconverter<58.6µs gives≈74µs, comfortably below0.5ms target; verify on bench. These analog RF/modulator-alias poles do not replace digital band filtering/anti-aliased decimation at51.2→25.6kS/s. No5ms analog fault smoothing. First-board acceptance: measured±1dB analog5Hz–5kHz,complete delay<0.5ms,±10V clipping/headroom,reference settling,noise,alias rejection anddriver stability.
Loads/procurement: ADC median5VA typical≈8.35mA withinputprecharge andtwofullreference buffers; sinc5 IOVDD≈1.97mA. QuadOPA typical4mA. DAC internalreference typical1.5mA. U28 normaltypical0.85mA at5.5V; allocate1.1mA per switch for prototype budget. Y1 current3mA typical at20MHz/3.3V plus CMOS load; startup3msmaximum. Engineering block reservations now 40mA5VA,15mA3V3A,3mAcarrier3V3, including driver/reference/load overhead; fit existing150/100/100mA rail budgets without power redesign. These are reservations, not a corner proof; measure rail current, startup andtemperature on firstboard. Prior LCSC snapshots are not reservations; AD7768 limitedstock andclock customconfiguration remain sourcing risks. Exact Y1 factory-configured frequency is13.107200MHz, CMOS,3.3V operation,OE function,2.5×2.0mm footprint; obtain authorized quote/programming confirmation, measure MCLK/jitter effects/noise. No user decision required to select this approved programmable-source route.
Fresh scoped ERC 2026-10-12T20:23:52.012Z:12Errors/3Warnings, versus follow-up baseline11/2: +1Error/+1Warning net. ResolvedAFE_DAC_RAW single-pin error; addedU28VDD andY1VCC MissingPower semantic reports on physicallyU8/U9-driven5VA/3V3A. AddedD9 unspecifiedpin Warning despite sourced verified1/2/3 polarity. Two remaining single-pin errors arefuturecarrierADC_DRDY_N/SPI_AFE_MISO; other preexistingerrors/warnings unchanged. Direct full50-net Block4 readback confirms protective source/drain direction,followers,matched subtraction,VCM loading,carrier-powered output clamp andclock. Nofloatingpin/short/driver-conflict issue in freshcheck. No fakepowerflags or suppression; not a cleanERC claim. Items1–5 completed atprototype schematic/documentation level; empirical acceptance/procurement andoverall project completion remain open. STOP here forBlock4 user review.
10. Prior verification and unresolved checks
Fresh final ERC2026-10-10T22:47:16.182Z 4Errors/2Warnings: U10/U11/U15VDD MissingPower errors onphysicallyU8/U9/U13drivenrails (librarypowersemantics unresolved), IC1IN_Aundriven despiteU6physicalconnection; IC1GND/X2bidirectional andD1unspecifiedpins warnings. No floatingpin/short/singlepinnet Error/Warning returned inERCquery. No suppressions/fakepowerflags. Targetednetreadback confirmsLT1763GND3/6/7, OUT-to-BYP, U14EN/ILIM/FAULTNC,U12FB/INTVCC,D6polarity, fivehealthyANDchain andRELEASEonlyU5MR. Two zero-member historicalSSnetobjects remain. No finalDRCclean/landpatternapproval claim; layoutunrouted.
Requiredbench:room/40°CLEDtrough≥4.5mA,commandopen≤1ms,eachpulseHIGH/LOW/stoppeddecay/independentACKtimeout,continuousPWMinhibit,9/12/24Vstartup/loadsteps,brownout/individualmissingrails/partialpower/backfeed,boot/reset/upload,thermal/inrush/hotLIsat/Ceff,roomcompleteoutputleakage≤10µA,panelisolationandfaultcoordination. No measuredresults; stuckpin decaynumericbound remainsunprovided. Five-rail supervisor hardware is built but must bequalified; lockinginlet,adapterloadreconciliation,recordingdurability andprofessional reviews beforeoverallcompletion. Current bounds/budgets/evidence in power-design-notes(sn),power-budget(eq), historicalcorrectivepass(0h). BoundedBlock2build cleanup ends here without more stages.
Final Blocks 8+9 controlling checkpoint — 2026-10-13