EntryD7TVS2700,D8SETclamp,C60compensation andbranchR40/R48nowwired. Nofeedback/U15/powerallocationchange; newleakagefits11mAHVreserve. Branch330ΩresistorsNOTinexcitationpath,no4mADCcomplianceloss. U13reference588–612mV and±10nA bias,actual422k/10k0.1%,giveconservative25.348–26.494Vstaticrailcorner beforedropout/ripple. Lowerrail−1.45Vallocatedsource dropout−≈0.21Vsettingdrop≈23.69V: >=24Vworst-caseconnectorrequirement BLOCKED,1.45Vat10mAnot4mAguarantee. D7stand-off27Vleaves≈0.506Vupperstaticmargin; noarbitraryrailincreasepermittedwithoutTVS/open-sensor/boostminimum/U13headroom/U15review. Sourcedmodestfeedbackrevisionaround26.3Vnominal iscandidateonly,notbuilt/qualified. Detailedconditions/evidence/benchgatein iepe-input-design-notes(l6); earlierentry-notbuiltstatementshistorical.

U23LT3092 excitation installed on26V_IEPE,4.010mAnominal; engineering screened3.842–4.178mA (conditional offset assumption,notguaranteedrange). Fits existing11mAHVgenerationreserve/90mAdigital5Vboostallowance; noallocationincrease,railfeedbackorU15change. Atshort25.92V×4.18mA≈108mWsourcepower;notthermalqualification. Nominalcompliance screen25.92−1.45−0.20=24.27Vbeforecable/protection;1.45Vmaxspecifiedat10mAnot4mA,railminimum/ripplecanconsumeallmargin. >=24Vconnectorgate unresolved; fullnotes/testcriteria in iepe-input-design-notes. Entryprotection/BNCblocked, Block3partial; earlier noexcitationinventory is superseded onlybythisaddition.

Final bounded Block2 cleanup, 2026-10-10, hardware commit 2b95c144. Readback: 160 components, 66 nets, 30 part types, 12 Functional Groups. This record supersedes older power topology statements, including shutdown-review power inventories. Schematic implementation is not completed Block2 qualification, board safety approval or authority for layout/order. No new layout, MCU, sensor/current-source, simulation or reviewer stage was undertaken.

X2 internal WAGO harness pin1 → F1 2A slow fuse → D4 SS310BF → VIN_PROTECTED; pin2 local GND. D5 SMBJ26A-Q shunts protected DC to GND. X2 is NOT a locking jack. IC3 LMR36520 produces digital5V; IC4 independent LMR36520 produces nominal6.988V 7V_PRE. Both have upstream VIN/EN, grounded PGND/EP, BOOT-to-SW capacitors, internal-VCC bypass and unused PG. Digital feedback100k/25k; analog pre-buck100k/16.7k. L1=10µH; L2=22µH; input banks4×4.7µF100V and output banks4×22µF25V each.

U7/U9 LT1763CS8-3.3#PBF, U8 LT1763CS8-5#PBF: U7 IN/SHDN5V → carrier3V3; U8/U9 IN/SHDN7V_PRE →5VA/3V3A. OUT1/SENSE2 tied respective output, GND3/6/7 all grounded, IN8 and SHDN5 upstream; BYP4 open on U7. C40/C41=10nF connect OUT-to-BYP, not GND. C24/C37/C39 exact CL32B226KAJNNNE22µF25V; input C23/C36/C38 generic4.7µF. Reverse protection with IN grounded is manufacturer-described; USB isolation is not thereby solved. Full-range output3.220–3.380V/4.875–5.125V applies only within datasheet conditions. Minimum Ceff3.3µF/ESR≤3Ω; analog bypass recommendation Ceff≥6.8µF. Nominal22µF does not establish biased/aged/temperature Ceff.

. U14 IN/EN5V, OUT limited node, ILIM via75k0.1% R32 toGND, #FAULT deliberately NC. L3=10µH; D6 SS16T3G anode SW/cathode28V_PRE. R28/R29=165k/10k sets nominal28V with1.60V reference. INTVCC C49=2.2µF toGND; C44=4.7µF100V limited-input bypass, C50=100nF digitalinput bypass. U13 LT3008 takes28V_PRE to nominal25.92V 26V_IEPE, existing422k/10k feedback and9.4µF nominal output. All three U13 GND pins grounded. This is generation, not 4mA excitation or ≥24V connector compliance.

U4 powered/MR tied digital5V, U10 powered/MR tied5VA, U11 powered/MR tied3V3A; SENSE is a divider of that same supply. U5 powered carrier3V3 and only U5 MR joins SHUTDOWN_RELEASE_N with default2.2k R5. Four TPS3808 RESETs each have own-rail47k pullup/1M bleed into U16–19 SN74LVC1G17 receivers. U15 TPS3842 powered by final26V_IEPE monitors that FINAL rail using340k/10k; RESET uses680k/100k into U20. Receivers and U21/U22 AND gates powered carrier3V3, each bypassed. U21 combines digital5V/5VA/3V3A; U22 combines U21 output/carrier3V3/finalIEPE. U22 Y → SHUTDOWN_POWER_OK with R45=10k default-low, U2 B and TP6. No common RESET wired-OR, no HV MR drive. CT open on four TPS3808; U15 CTS open, CTR C59=5.6nF5%.

Truth table: RELEASE low → U5 unhealthy/inhibit; any one of five rails unhealthy/absent → AND permission low once its detector/receiver is valid; all five healthy and RELEASE high for release delays → permission MAY qualify, still requiring independent pulses/trip permissions. Carrier0 → receiver/gate outputs unpowered/high-Z and final10k pulldown inhibits. This is intended and DC-screened behavior, not ramp/backfeed/command-latency certification. Upstream enables remain on; inhibited does not turn off analog/IEPE generation. Receiver outputs have no individual pulldowns; final permission alone has10k. Ioff and final leakage/default-low behavior require full startup testing, not imaginary individual pull resistors. Receiver recommended input≤5.5V independent of powered-off supply and Ioff≤10µA.

U15 divider U20 input at28.8V assumed HV upper operating envelope,0.1% resistors and adverse10µA off leakage is ≤4.572V, below5.5V even with carrier0. This is not proof for arbitrary HV fault: divider/leakage reaches5.5V near36.0V, below detector42V rating. Keep receiver-node≤5.5V as explicit fault gate. Absent HV local rail with+5µA input leakage gives≈0.436V, or≈0.873V using10µA powered-off leakage. Four47k/1M low-voltage interfaces at3.220V and5.3µA adverse combined leakage screen Vhigh≈2.84V; absent own rail with5µA gives≈0.224V. Exact3.3V Schmitt threshold is not tabulated; published3V/4.5V rows and partial-power startup require bench acceptance.

TPS3808 adjustable reference0.405V ±2%, hysteresis≤3%, SENSE current±25nA, divider0.1% corners. For each divider: falling minimum uses0.98 reference, top0.999/bottom1.001 and subtract25nA×topmax; rising maximum uses1.02 reference×1.03 hysteresis, top1.001/bottom0.999 and adds25nA×topmax.

U4 versus provisional buck low4.92V leaves57.92mV release margin; allocating10mV peak ripple leaves47.92mV. Falling margin over TC4427 minimum4.5V is13.81mV;10mV ripple leaves 3.81mV for additional droop during detector response. Thus dynamic droop cannot be assumed safe: numeric compatibility gate is remaining transient≤3.81mV under that allocation or reassess before EE release. U5 versus LT1763 guaranteed3.220V leaves55.77mV rise margin,45.77mV after10mV ripple. Allocate critical carrier digital minimum2.9V, NOT3.0V or ADC-power guarantee: fallmin minus10mV ripple=2.92830V leaves28.30mV transient margin above2.9V. IC2 minimum2.25V/U2 minimum1.65V and translator supply compatibility are retained requirements, not a newly proven MCU reset contract. Analog U11 rise margin only23.53mV,13.53mV after10mV ripple; not changed or noise/ADC-qualified in this bounded pass.

Four TPS3808 CT-open release delays 12–28ms (20ms nominal), not10ms guaranteed. MR/SENSE assertion delays150ns/20µs are typical, not worst-case shutdown bounds. U15 CTR equations tmin=2×Cmin, ttyp=2.858×Ctyp, tmax=3.715×Cmax with C inµF/time seconds yield 10.64/16.005/21.844ms, before parasitics/leakage/temperature capacitance beyond5% assumption. All-five-rail release can take max28ms plus receiver/gate settling after the last rail/MR qualifies; system command-open≤1ms is separate and still unmeasured.

R5 low ratio now2222/(70000+2222)=0.03077 with ONE MR pullup; high source≤3.380/2178=1.552mA excluding leakage and assuming bounded local carrier source. Existing shutdown isolation/output paths unchanged.

See current power-budget: digital5V peak1.000A includes generation90mA and additional allowance10mA; 7V_PRE253mA includes analog250mA plus3mA overhead, not old310mA/7V boost load. At9V jack/8V protected reflectedpeak1.0234A, at12V/11V0.7443A, assumed85% buck. Regulated12V adapter≥1.5A remains procurement recommendation, actual adapter unconfirmed. Detailed efficiency/typical reserves are not measured consumption.

R32 current-limit hand bounds≈314/353/397mA. 28V×11mA/(4.8V×75%)=85.6mA normal boost input; inductivecrest≈220mA atLmin/fmin. TPS2553 thermal retry is not a latch; response2µs is typical. D6 rated1A average under case-temperature condition;40A nonrepetitive surge is not repeated-short safety. Output bank nominal stored energy≈6.862mJ (C45/C46≈3.685mJ at28V, C47/C48≈3.177mJ at26V), plus C44/INTVCC/inductive/source-fed energy and tolerances. Full short peak, energy/overshoot, repeated heating and postfault recovery remain EE/first-board gates.

Ceff, ESR/ripple/loadstep/loop stability, hot Isat, D4≈0.870W low-input peak-reference heating, LDO copper/enclosure and boost minimum/headroom over U13 max/dropout/ripple remain gates. No qualified ≥24V connector, clean-noise, USB isolation, sustained wrongadapter or fault-safe branch claim. Bench first with current-limited source; missing-rail/RELEASE/inhibit/startup/loadstep checks at9/12/24V and40°C; destructive short tests only after unresolved stored-energy/overshoot review.

Exact candidate pair Kycon KLDPLX-0202-B / KLDLX-P-0202-B-M8, or Switchcraft L712A /761K (not712A). No jack imported/placed; terminal-number→center/sleeve/switch mapping and import/footprint unresolved. X2 internal harness is not jack. No new research loop. Kycon pair Kycon drawing Switchcraft mates

2026-10-10T22:47:16.182Z ERC 4 Errors/2 Warnings: U10/U11/U15 VDD Missing Power, although physically fed U8/U9/U13 OUT; these library-power-semantic findings remain errors, not suppressed/hidden. IC1 IN_A undriven despite U6 physical driver remains error. IC1 GND/X2 bidirectional and D1 unspecified-pin warnings remain. No floating-pin/short/single-pin-net Error/Warning returned. Targeted readback confirms diode polarity, U14 pins, U12 feedback/INTVCC, three LT1763 GND pins each and OUT-to-BYP. Two empty old analog SS net objects remain zero-member and harmless; not removed because no topology repair required. No DRC-clean claim.

Completion: records/readback/threshold edits completed; real floating/wrong pins not found in target scope. Locking inlet remains failed qualification/unattempted import; bench/procurement safety qualification incomplete. Historical initial-stop detail remains explicitly historical in power-corrective-pass (0h). This ends the bounded cleanup, not the overall design.