Battery Converter Design


Fresh review result
A fresh paginated Overlapping Copper review returned 276 current findings. The project has a global rule applying 0.15 mm keepout to traces, pads, vias, fills, polygons, and nets, so this review is not limited to different-net shorts. It also reports intentional same-net trace–pad, trace–via, and branch junctions.
The DRC response provides object UIDs but not the net of each route segment. Therefore, a complete net-by-net classification of all 276 pairs is not directly available. The following is an exact, conservative attribution ledger: findings with recognizable component-pad UIDs are assigned to functional clusters; everything else remains in cluster 6 as requested.
Exact conservative counts

Table


#Functional clusterDirectly attributableNotes
1Potentiostat analog drive/current sense/reference/AGND3U_DAC/AGND and AGND–DGND link contacts
2Fault/current-limit/load-detect/shutdown12All are around U_FAULT_LATCH
3USB-C and power regulation9J_USB shell plus U_LDO_D/U_LDO_A
4Arduino/OLED/encoder/digital control8ADC alert, FTDI, Arduino/OLED grounds, encoder mount
5SMB connectors/INT-EXT selector/output connectors1Directly identified J_SMB_RE shell-pad contact
6Same-net trace-pad/via artifacts or unclassified UID-only findings243Route/via/pad findings lacking enough net metadata
Total276Exact current DRC total
These are lower bounds for clusters 1–5, not a claim that only those findings physically occur in those areas. Cluster 6 absorbs every pair that could not be safely assigned without inventing a route UID → net mapping.

Cluster details and representative pairs 1. Analog drive/current sense/reference/AGND — 3
Representative pairs:
  • U_DAC:~LDAC~
    02b33325…__b7589d9c… ↔ Trace 05f949ac…
  • R_AGND_DGND:P1
    7a2ef6c8…__dff57d78… ↔ Trace 6d968da8…
  • R_AGND_DGND:P1
    7a2ef6c8…__dff57d78… ↔ Trace f3f05564…
Classification: The ~LDAC~ contact is known to be an AGND same-net pad-entry artifact. The two star-link resistor endpoint contacts also look like intentional route-to-pad entries under the global keepout rule. No current different-net analog short is proven from these three pairs alone.
Highest-risk analog items among the unclassified population: dense trace interaction groups headed by Trace 238d (six pairs), 271b (seven), 017c (ten), and 7f6d (four) should not be dismissed merely because many other findings are artifacts; their nets are absent from the DRC payload.

2. Fault/current-limit/load-detect/shutdown — 12
All twelve directly identified findings involve U_FAULT_LATCH:
  • ~Q2 ↔ Trace 971c1df2…1
  • ~Q1 ↔ Traces 390c3a33…, a62859dc…2
  • RESET1 ↔ Traces 390c3a33…, 3f29e212…, 4f4ccedc…, a62859dc…4
  • SET1 ↔ Traces 3f29e212…, 4f4ccedc…, c7b8f58b…, e2abafba…, ecb87307…5
Risk distinction:
  • The three ~Q1/~Q2 contacts are the highest-risk representatives. Those latch outputs have previously appeared as logically unused/no-connect outputs; copper touching them should be treated as a credible real risk until net identity is verified.
  • The nine RESET1/SET1 pairs form repeated pad/branch networks and are much more characteristic of same-net trace–pad/trace–trace keepout artifacts.
  • Current-limit, load-detect, and shutdown route-only findings are included in the 243 unclassified count because their trace UIDs cannot be safely tied to nets from the DRC response.

3. USB-C and power regulation — 9
Representative pairs:
  • U_LDO_D:NC
    31161b42…__30f3e345… ↔ Trace 3e0f0717…
  • U_LDO_D:EN
    31161b42…__9a6ce0c6… ↔ Trace 091187a2…
  • U_LDO_A:OUT
    9c206145…__5ad4e767… ↔ Trace 122a5ed1…
  • U_LDO_A:GND
    9c206145…__8c60cffa… ↔ Trace 1e9a82ee…
  • J_USB:S1 shell/mount pad
    8bbcaffd…mounts.21c2dc92… ↔:
    • Trace 00c9b93a…
    • Trace 534bbe72…
    • Trace 6cbf7b65…
    • Trace cb954fac…
    • Trace df47c909…
Risk distinction:
  • Highest risk: U_LDO_D:NC ↔ Trace 3e0f. A routed copper object touching an NC pad is not an ordinary intended junction.
  • The five J_USB:S1 contacts are credible shell/mount-pad risks, because S1 is a footprint shell pad rather than one of the explicitly named GND_A/GND_B signal pads. They may be intentional shell grounding, but the current logical data does not prove that.
  • The EN, OUT, and GND pairs look like normal pad entries and are likely artifacts unless the paired trace is shown to carry another net.

4. Arduino/OLED/encoder/digital control — 8
Directly attributable findings:
  • U_ADC:ALERT/RDY ↔ Trace 1fc1dbad…1
  • J_FTDI:Pin_6 ↔ Trace a7e275a8…1
  • J_FTDI:Pin_1 ↔ Trace 343116ad…1
  • OLED1:GND ↔ Trace 4ea4338f…1
  • Two U_ARD:GND pads ↔ Trace 90e09d93…, plus one ↔ Trace a99c449f…3
  • ENC1:P$6 mechanical mount ↔ Trace ee2aa7d7…1
Risk distinction:
  • U_ADC:ALERT/RDY ↔ Trace 1fc1 is a confirmed same-net ADC_ALERT pad-entry artifact.
  • OLED and Arduino GND contacts are strongly consistent with same-net ground-entry artifacts.
  • The encoder mechanical mount ↔ Trace ee2a is the highest-risk digital representative because the mount is not an ordinary signal pad.
  • FTDI Pin 1/6 contacts require route-net verification; they may simply be normal pad entries.

5. SMB connectors/INT-EXT selector/output connectors — 1 directly attributable
  • J_SMB_RE:2 shell pad
    0d88c73c…__78f5c63d… ↔ Trace a3b89a5d…
Pad 2 is one of the four SMB shell holes; pad 1 is the center conductor.
Classification: This is the highest-risk directly identified connector pair. It is harmless only if Trace a3b89a5d is on SMB_SHIELD_STAR; otherwise it is a real center/signal-to-shell-area clearance problem.
Many generic through-hole and P1/P2 reports almost certainly belong to SMB, selector, or output connectors, but their owning component is not encoded in the DRC check name and they therefore remain in cluster 6.

6. Same-net junction artifacts or unclassified — 243
This bucket contains all UID-only findings that cannot be truthfully assigned to a functional net from the review output. It includes:
  • Trace–pad endpoint contacts
  • Trace–via and trace–through-hole transitions
  • Trace–trace branches and collinear joins
  • Ground contacts
  • Mechanical/mount-pad contacts
  • Possible genuine different-net crossings
Representative dense interaction groups:
  • Trace 017c10 reported neighbors
  • Trace 271b7
  • Trace 238d6
  • Trace 15545
  • Trace 33b15
  • Trace 83fc5
  • Trace 7f6d4
  • Trace 4f4c4
  • Trace 6da84
These are the best candidates for manual net comparison because a single route object contacting many copper objects can indicate either a normal multi-branch same-net junction or a route passing through an unrelated cluster.

True-risk versus keepout-artifact conclusion Credible current different-net or unintended-copper risks
Not conclusively net-proven by the DRC payload, but should be treated as real until checked:
  1. U_LDO_D:NC ↔ Trace 3e0f
  2. U_FAULT_LATCH:~Q2 ↔ Trace 971c
  3. U_FAULT_LATCH:~Q1 ↔ Traces 390c, a628
  4. J_USB:S1 ↔ five traces
  5. J_SMB_RE:2 ↔ Trace a3b8
  6. ENC1:P$6 mount ↔ Trace ee2a
  7. Dense route-only groups such as 017c, 271b, 238d, and 83fc
Confirmed or strongly indicated 0.15 mm-rule artifacts
  • U_DAC:~LDAC~ ↔ Trace 05f9 — same-net AGND
  • U_ADC:ALERT/RDY ↔ Trace 1fc1 — same-net ADC_ALERT
  • Repeated RESET1 and SET1 route contacts
  • Arduino/OLED GND pad entries
  • Most ordinary trace-to-pad and trace-to-via endpoint reports
Bottom line
  • Current exact total: 276
  • An exact non-overlapping accounting is provided above: 3 + 12 + 9 + 8 + 1 + 243 = 276
  • The broad 0.15 mm global copper keepout rule is clearly inflating the review with same-net junction findings.
  • The review cannot establish a precise true-short count because it omits route-segment net names. The NC, unused latch-output, shell/mount-pad, and dense multi-contact cases are the findings that should not be written off as rule artifacts.
No project changes were made.Current PCBWay-rule review reports 276, not 163, overlap findings:
  • Analog drive/sense/reference: 3
  • Fault/current-limit/shutdown: 12
  • USB-C/power regulation: 9
  • Arduino/OLED/digital: 8
  • SMB/selector connectors: 1
  • Same-net junction artifacts or unclassified trace-only pairs: 243
Highest-risk repairs:
  1. Potentiostat Kelvin/sense airwires: WE_DRV, WE_INT, I_SENSE_POS/NEG, I_SENSE, and references.
  2. Copper touching U_LDO_D:NC and unused U_FAULT_LATCH:~Q1/~Q2.
  3. USB shell/mount contacts, SMB shell contact, and encoder mounting-pad contact.
  4. Dense trace groups 017c, 271b, 238d, and 83fc.
Most findings are inflated by the global 0.15 mm keepout treating legal same-net junctions as overlaps. 120 × 120 mm is not necessary: board occupancy is only 33.6%; the rule definition and incomplete routing are the primary issues. No resize was applied. Further project work is paused because no ACUs are currently available.
Fix highest-risk violations
Clean up all findings
Reclassify junction artifacts
Inspect U_ARD violations
Check remaining blockers

U_LDO_D
J_POST_CE
U_LDO_A
J_POST_WE
J_POST_RE
U_REF A - U_DAC AVSS
LED_LOAD K - Q_LED C
U_LDO_D OUT - C_LDO_D_OUT P1
U_REF A - U_DAC AVSS
U_BOOST VOUT - C_BOOST_OUT1 P1
U_ARD A5 - U_ADC SCL
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
R_REF_BIAS P2 - U_REF K
S_INT_EXT NO_3 - J_POST_CE 1
R_REF_BIAS P2 - U_REF K
S_INT_EXT NO_2 - J_POST_RE 1
U_ARD D5 - R_SHDN_SER P1
R_SENSE P2 - U_OUT -
U_DAC VoutA - U_OUT +
U_BOOST VOUT - C_BOOST_OUT1 P1
J_FTDI Pin_5 - U_ARD TXO
S_INT_EXT NO_2 - J_POST_RE 1
U_REF A - U_DAC AVSS
U_REF A - U_DAC AVSS
R_LED P2 - LED_LOAD A
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
U_REF A - U_DAC AVSS
U_ARD D10 - U_DAC ~CS~
R_SNS_NONINV P2 - R_SNS_REF P1
S_INT_EXT COM_1 - J_SMB_WE 1
R_SENSE P2 - U_OUT -
R_SHDN_SER P2 - R_SHDN_PD P1
F_USB ~ - D_USB_TVS 1
U_BOOST VOUT - C_BOOST_OUT1 P1
U_REF A - U_DAC AVSS
R_SNS_NONINV P2 - R_SNS_REF P1
R_REF_BIAS P2 - U_REF K
R_SHDN_SER P2 - R_SHDN_PD P1
D_FAULT_SRC K - D_FAULT_SINK K
S_INT_EXT NO_3 - J_POST_CE 1
U_BOOST VOUT - C_BOOST_OUT1 P1
S_INT_EXT 12 - Q_SHDN S
U_LDO_D OUT - C_LDO_D_OUT P1
J_FTDI Pin_4 - U_ARD RXI
J_FTDI Pin_6 - C_FTDI_DTR P1
U_ARD D2 - ENC1 A
S_INT_EXT NO_3 - J_POST_CE 1
R_REF_MID_TOP P2 - R_REF_MID_BOT P1
U_LD_SRC OUT - D_LD_SRC A
S_INT_EXT NO_1 - J_POST_WE 1
U_LDO_D OUT - C_LDO_D_OUT P1
U_BOOST VOUT - C_BOOST_OUT1 P1
U_LDO_A EN - C_LDO_D_IN P1
U_ARD MOSI - U_DAC SDI
U_ARD D4 - ENC1 S2
S_INT_EXT COM_3 - J_SMB_CE 1
J_FTDI Pin_4 - U_ARD RXI
R_ILIM_LO_TOP P2 - R_ILIM_LO_BOT P1
U_ARD D4 - ENC1 S2
U_ARD D2 - ENC1 A
S_INT_EXT NO_1 - J_POST_WE 1
R_LED P2 - LED_LOAD A
S_INT_EXT NO_1 - J_POST_WE 1
S_INT_EXT NO_3 - J_POST_CE 1
R_ILIM_HI_TOP P2 - R_ILIM_HI_BOT P1
C_FTDI_DTR P2 - U_ARD RST_1
J_USB CC1 - R_CC1 P1
C_FTDI_DTR P2 - U_ARD RST_1
S_INT_EXT NO_1 - J_POST_WE 1
R_REF_BIAS P2 - U_REF K
R_LD_LO_TOP P2 - R_LD_LO_BOT P1
S_INT_EXT NO_3 - J_POST_CE 1
S_INT_EXT NO_1 - J_POST_WE 1
D_LD_SRC K - D_LD_SINK K
U_LDO_D OUT - C_LDO_D_OUT P1
S_INT_EXT NO_3 - J_POST_CE 1
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
U_BOOST VOUT - C_BOOST_OUT1 P1
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
U_REF A - U_DAC AVSS
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
S_INT_EXT COM_2 - J_SMB_RE 1
U_LD_SINK OUT - D_LD_SINK A
U_ARD D6 - U_FAULT_LATCH RESET1
U_REF A - U_DAC AVSS
R_REF_BIAS P2 - U_REF K
S_INT_EXT NO_3 - J_POST_CE 1
U_ARD D10 - U_DAC ~CS~
U_BOOST VOUT - C_BOOST_OUT1 P1
U_ADC ALERT/RDY - U_ARD D7
U_LDO_D OUT - C_LDO_D_OUT P1
U_LDO_D OUT - C_LDO_D_OUT P1
S_INT_EXT NO_1 - J_POST_WE 1
U_ARD D5 - R_SHDN_SER P1
U_REF A - U_DAC AVSS
U_BOOST VOUT - C_BOOST_OUT1 P1
U_ARD SCK - U_DAC SCK
U_REF A - U_DAC AVSS
U_LDO_D OUT - C_LDO_D_OUT P1
S_INT_EXT NO_3 - J_POST_CE 1
S_INT_EXT NO_1 - J_POST_WE 1
U_REF A - U_DAC AVSS
U_LDO_D OUT - C_LDO_D_OUT P1
U_BOOST VOUT - C_BOOST_OUT1 P1
U_REF A - U_DAC AVSS
R_LED_BASE P2 - R_LED_BASE_PD P1
U_ARD D3 - ENC1 B
R_ILIM_HI_TOP P2 - R_ILIM_HI_BOT P1
U_ARD MOSI - U_DAC SDI
J_SMB_WE 5 - J_SMB_RE 2
S_INT_EXT NO_2 - J_POST_RE 1
U_ARD A4 - U_ADC SDA
S_INT_EXT NO_1 - J_POST_WE 1
D_FAULT_SRC K - D_FAULT_SINK K
U_LDO_D OUT - C_LDO_D_OUT P1
S_INT_EXT COM_1 - J_SMB_WE 1
U_REF A - U_DAC AVSS
S_INT_EXT NO_3 - J_POST_CE 1
U_REF A - U_DAC AVSS
U_BOOST VOUT - C_BOOST_OUT1 P1
D_LD_SRC K - D_LD_SINK K
U_REF A - U_DAC AVSS
S_INT_EXT NO_3 - J_POST_CE 1
J_USB CC2 - R_CC2 P1
S_INT_EXT NO_3 - J_POST_CE 1
U_OUT ~ - R_SENSE P1
U_REF A - U_DAC AVSS
U_LDO_D OUT - C_LDO_D_OUT P1
R_SENSE P2 - U_OUT -
F_USB ~ - D_USB_TVS 1
F_USB ~ - D_USB_TVS 1
S_INT_EXT NO_1 - J_POST_WE 1
U_REF A - U_DAC AVSS
LED_LOAD K - Q_LED C
S_INT_EXT COM_3 - J_SMB_CE 1
J_SMB_RE 5 - J_SMB_CE 2
F_USB ~ - D_USB_TVS 1
U_REF A - U_DAC AVSS
R_REF_BIAS P2 - U_REF K
U_ARD A5 - U_ADC SCL
S_INT_EXT NO_1 - J_POST_WE 1
R_SENSE P2 - U_OUT -
U_ARD D6 - U_FAULT_LATCH RESET1
U_REF A - U_DAC AVSS
S_INT_EXT NO_2 - J_POST_RE 1
R_REF_BIAS P2 - U_REF K
U_BOOST VOUT - C_BOOST_OUT1 P1
S_INT_EXT NO_2 - J_POST_RE 1
R_LD_LO_TOP P2 - R_LD_LO_BOT P1
S_INT_EXT NO_2 - J_POST_RE 1
U_ARD D2 - ENC1 A
D_LD_SRC K - D_LD_SINK K
U_REF A - U_DAC AVSS
S_INT_EXT NO_1 - J_POST_WE 1
J_SMB_WE 5 - J_SMB_RE 2
U_ILIM_SINK OUT - D_FAULT_SINK A
U_LDO_D EN - U_LDO_A IN
U_ILIM_SINK OUT - D_FAULT_SINK A
U_REF A - U_DAC AVSS
S_INT_EXT NO_2 - J_POST_RE 1
S_INT_EXT NO_2 - J_POST_RE 1
R_LED_BASE P2 - R_LED_BASE_PD P1
J_SMB_CE 5 - R_SMB_SHIELD_STAR P1
S_INT_EXT NO_1 - J_POST_WE 1
U_REF A - U_DAC AVSS
U_LDO_D OUT - C_LDO_D_OUT P1
S_INT_EXT NO_1 - J_POST_WE 1
R_REF_MID_TOP P2 - R_REF_MID_BOT P1
S_INT_EXT NO_2 - J_POST_RE 1
U_REF A - U_DAC AVSS
U_REF A - U_DAC AVSS
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
R_LD_HI_TOP P2 - R_LD_HI_BOT P1
U_REF A - U_DAC AVSS
J_USB VBUS_A - J_USB VBUS_B
U_ARD D4 - ENC1 S2
U_ILIM_SRC OUT - D_FAULT_SRC A
R_REF_BIAS P2 - U_REF K
U_FAULT_LATCH Q1 - Q_SHDN G
U_DAC VoutA - U_OUT +
S_INT_EXT NO_1 - J_POST_WE 1
U_ARD D6 - U_FAULT_LATCH RESET1
J_SMB_CE 5 - R_SMB_SHIELD_STAR P1
F_USB ~ - D_USB_TVS 1
U_REF A - U_DAC AVSS
R_ILIM_HI_TOP P2 - R_ILIM_HI_BOT P1
D_LD_SRC K - D_LD_SINK K
U_REF A - U_DAC AVSS
U_FAULT_LATCH Q1 - Q_SHDN G
U_REF A - U_DAC AVSS
S_INT_EXT NO_2 - J_POST_RE 1
U_ADC ALERT/RDY - U_ARD D7
U_LDO_D OUT - C_LDO_D_OUT P1
U_LDO_A EN - C_LDO_D_IN P1
R_REF_BIAS P2 - U_REF K
R_LD_HI_TOP P2 - R_LD_HI_BOT P1
U_ARD D3 - ENC1 B
U_ARD A4 - U_ADC SDA
U_OUT ~ - R_SENSE P1
S_INT_EXT NO_2 - J_POST_RE 1
S_INT_EXT NO_1 - J_POST_WE 1
R_SENSE P2 - U_OUT -
R_SHDN_SER P2 - R_SHDN_PD P1
U_OUT ~ - R_SENSE P1
U_REF A - U_DAC AVSS
S_INT_EXT NO_3 - J_POST_CE 1
R_SENSE P2 - U_OUT -
R_LD_LO_TOP P2 - R_LD_LO_BOT P1
J_FTDI Pin_5 - U_ARD TXO
U_LDO_D EN - U_LDO_A IN
D_FAULT_SRC K - D_FAULT_SINK K
R_SNS_NONINV P2 - R_SNS_REF P1
U_ILIM_SRC OUT - D_FAULT_SRC A
S_INT_EXT 12 - Q_SHDN S
J_FTDI Pin_6 - C_FTDI_DTR P1
S_INT_EXT COM_2 - J_SMB_RE 1
S_INT_EXT NO_3 - J_POST_CE 1
U_ARD A4 - U_ADC SDA
U_LDO_D OUT - C_LDO_D_OUT P1
U_DAC VoutA - U_OUT +
U_LD_SRC OUT - D_LD_SRC A
R_LD_HI_TOP P2 - R_LD_HI_BOT P1
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
S_INT_EXT NO_2 - J_POST_RE 1
S_INT_EXT NO_3 - J_POST_CE 1
R_ILIM_LO_TOP P2 - R_ILIM_LO_BOT P1
S_INT_EXT 12 - Q_SHDN S
J_SMB_RE 5 - J_SMB_CE 2
J_USB CC2 - R_CC2 P1
U_LD_SINK OUT - D_LD_SINK A
R_REF_BIAS P2 - U_REF K
J_USB CC1 - R_CC1 P1
U_REF A - U_DAC AVSS
U_BOOST VOUT - C_BOOST_OUT1 P1
S_INT_EXT NO_2 - J_POST_RE 1
S_INT_EXT NO_3 - J_POST_CE 1
U_LDO_D OUT - C_LDO_D_OUT P1
J_USB VBUS_A - J_USB VBUS_B
R_SNS_INV P2 - R_SNS_FB P2
U_REF A - U_DAC AVSS
U_BOOST VOUT - C_BOOST_OUT1 P1
S_INT_EXT NO_2 - J_POST_RE 1
D_FAULT_SRC K - D_FAULT_SINK K
C_FTDI_DTR P2 - U_ARD RST_1
S_INT_EXT NO_2 - J_POST_RE 1
U_OUT ~ - R_SENSE P1
U_LDO_D OUT - C_LDO_D_OUT P1
U_REF A - U_DAC AVSS
F_USB ~ - D_USB_TVS 1
S_INT_EXT NO_1 - J_POST_WE 1
U_ARD D10 - U_DAC ~CS~
S_INT_EXT NO_3 - J_POST_CE 1
U_BOOST VOUT - C_BOOST_OUT1 P1
U_FAULT_LATCH Q1 - Q_SHDN G
U_ILIM_SRC IN+ - U_ILIM_SINK IN-
R_REF_MID_TOP P2 - R_REF_MID_BOT P1
U_BOOST VOUT - C_BOOST_OUT1 P1
S_INT_EXT 12 - Q_SHDN S
S_INT_EXT NO_1 - J_POST_WE 1
R_LED_BASE P2 - R_LED_BASE_PD P1
U_ARD A4 - U_ADC SDA
R_SNS_INV P2 - R_SNS_FB P2
R_REF_MID_TOP P2 - R_REF_MID_BOT P1
U_ARD SCK - U_DAC SCK
S_INT_EXT NO_2 - J_POST_RE 1
U_BOOST VOUT - C_BOOST_OUT1 P1
U_FAULT_LATCH Q1 - Q_SHDN G
R_SHDN_SER P2 - R_SHDN_PD P1
S_INT_EXT NO_3 - J_POST_CE 1
R_ILIM_LO_TOP P2 - R_ILIM_LO_BOT P1
J_USB VBUS_A - J_USB VBUS_B
R_SNS_INV P2 - R_SNS_FB P2
S_INT_EXT 12 - Q_SHDN S
U_ARD A5 - U_ADC SCL
U_ARD A5 - U_ADC SCL
R_REF_MID_TOP P2 - R_REF_MID_BOT P1
U_ARD D3 - ENC1 B
R_SHDN_SER P2 - R_SHDN_PD P1
S_INT_EXT NO_2 - J_POST_RE 1
U_DAC
U_REF
R_REF_MID_BOT
Resistance
100kΩ
R_ILIM_LO_TOP
Resistance
291kΩ
R_SHDN_PD
Resistance
100kΩ
R_REF_MID_TOP
Resistance
100kΩ
R_LD_HI_TOP
Resistance
98.1kΩ
R_CC1
Resistance
5.1kΩ
R_LED_BASE
Resistance
100kΩ
R_ENC_SW_PU
Resistance
10kΩ
R_ENC_A_PU
Resistance
10kΩ
R_SNS_INV
Resistance
20.0kΩ
R_SNS_FB
Resistance
100kΩ
R_I2C_SCL
Resistance
4.7kΩ
R_LD_HI_BOT
Resistance
100kΩ
R_AGND_DGND
Resistance
R_DAC_CS_PU
Resistance
10kΩ
R_ILIM_HI_BOT
Resistance
100kΩ
R_LD_LO_BOT
Resistance
100kΩ
R_ILIM_LO_BOT
Resistance
100kΩ
R_ENC_B_PU
Resistance
10kΩ
R_FAULT_SET_PD
Resistance
100kΩ
R_ILIM_HI_TOP
Resistance
34.4kΩ
R_LD_LO_TOP
Resistance
102kΩ
R_I2C_SDA
Resistance
4.7kΩ
R_SNS_NONINV
Resistance
20.0kΩ
R_SMB_SHIELD_STAR
Resistance
R_REF_BIAS
Resistance
4.99kΩ
R_CC2
Resistance
5.1kΩ
R_FAULT_RST_PD
Resistance
100kΩ
R_LED
Resistance
2.2kΩ
R_QSHDN_GPD
Resistance
1.0MΩ
R_SENSE
Resistance
10.0Ω
R_SHDN_SER
Resistance
1.0kΩ
R_LED_BASE_PD
Resistance
1.00MΩ
R_LED_OR_PD
Resistance
100kΩ
R_SNS_REF
Resistance
100kΩ
J_FTDI
U_FAULT_LATCH RESET2 - R_FAULT_SET_PD P2
J_SMB_RE
U_LD_SINK
ENC1 C - ENC1 S1
J_USB GND_A - J_USB GND_B
U_ARD GND_2 - C_ARD P2
GND
U_LD_SRC
J_USB GND_A - J_USB GND_B
J_USB GND_A - J_USB GND_B
U_ILIM_SRC
J_USB GND_A - J_USB GND_B
J_USB GND_A - J_USB GND_B
R_AGND_DGND P2 - C_ARD P2
U_ARD GND_2 - C_ARD P2
J_USB GND_A - J_USB GND_B
ENC1 C - ENC1 S1
U_FAULT_LATCH RESET2 - R_FAULT_SET_PD P2
OLED1 GND - U_DAC ~LDAC~
U_FAULT_LATCH RESET2 - R_FAULT_SET_PD P2
R_AGND_DGND P2 - C_ARD P2
J_USB GND_A - J_USB GND_B
J_SMB_CE
J_SMB_WE
U_FAULT_LATCH CLOCK1 - U_FAULT_LATCH D2
J_USB GND_A - J_USB GND_B
R_LED_OR_PD P2 - R_LED_BASE_PD P2
R_LED_OR_PD P2 - R_LED_BASE_PD P2
J_USB GND_A - J_USB GND_B
U_FAULT_LATCH CLOCK1 - U_FAULT_LATCH D2
GND
U_ILIM_SINK
R_LED_OR_PD P2 - R_LED_BASE_PD P2
J_USB GND_A - J_USB GND_B
J_USB GND_A - J_USB GND_B
C_LD_FILTER
Capacitance
1nF
C_REF
Capacitance
100nF
C_LDO_D_OUT
Capacitance
1µF
LED_LOAD
C_FTDI_DTR
Capacitance
100nF
C_SENSE_AMP
Capacitance
100nF
C_LDO_A_OUT
Capacitance
1µF
C_3V3D_BULK
Capacitance
10µF
C_DAC_REF
Capacitance
100nF
C_OUT_AMP
Capacitance
100nF
C_LDO_A_IN
Capacitance
1µF
C_USB_HF
Capacitance
100nF
C_LDO_D_IN
Capacitance
1µF
C_ARD
Capacitance
100nF
C_OUT
Capacitance
1nF
C_REF_MID
Capacitance
100nF
C_ADC
Capacitance
100nF
C_ILIM_FILTER
Capacitance
1nF
C_DAC
Capacitance
100nF
C_USB_BULK
Capacitance
47µF
C_3V3A_BULK
Capacitance
10µF
OLED1
U_FAULT_LATCH
U_ARD
Q_LED
F_USB
U_ADC
U_OPA
Q_SHDN
U_OUT
J_USB
D_LD_SINK
ENC1
D_FAULT_SINK
D_LD_SRC
D_FAULT_SRC
S_INT_EXT
D_USB_TVS
Routing Stop Report — Critical Nets and Ground Split Blocker
Why routing stopped
Routing was stopped before bulk autoroute because the available bulk router routes the whole board, including GND. With the current single schematic GND net and existing full-board GND fill, I cannot guarantee the Rev 2 requirement of separate analog/digital ground pours joined at exactly one point near the analog LDO/reference, nor can I guarantee no extra SMB_SHIELD_STAR/GND stitching if bulk autoroute is allowed to proceed.
This is a grounding-integrity blocker, not a schematic blocker.
Work completed before stopping
  • BOM correction: U_REF manufacturer part number updated to LM4040A20IDBZR, Texas Instruments LM4040A 2.048 V A-grade 0.1% SOT-23/DBZ reference.
  • Confirmed R_SENSE is already specified as 10.0 Ω, 0.1%, 0603, 0.1 W.
  • Filed a Flux missing-part request for LM4040A20IDBZR because the library exposed only D-grade LM4040 records.
  • Re-clustered the OPA2333 sense-input resistors so Kelvin taps can be routed from the 10 Ω shunt pads with short matched branches.
  • Manually routed the critical Kelvin/output/sense/reference traces before any bulk routing:
    • WE_DRV shunt-side load path and Kelvin branch
    • WE_INT shunt-side Kelvin branch and feedback/ADC monitor branches
    • I_SENSE_POS
    • I_SENSE_NEG
    • local I_SENSE feedback/output segment
    • VREF_2V048 LM4040-to-DAC/reference-bypass path
    • DAC_VSET
    • OPA_B_FOLLOWER
    • local VREF_MID_1V024
    • local OPA2333 decoupling traces
  • Router preflight was made clean for generic routability after manually handling fine-pin blockers.
What is not complete
  • Full-board routing is not complete.
  • Airwires remain on non-critical nets.
  • DRC is not clean because routing is incomplete and some manually drawn traces still need final overlap/clearance review.
  • Manufacturing outputs were not generated.
Required next decision
To finish routing safely, choose one of these paths:
  1. Schematic/net split approach (recommended): split ground into explicit AGND, DGND, and SMB_SHIELD_STAR domains, connect AGND/DGND at one net-tie or 0 Ω link near the analog LDO/reference, then route/fill each domain explicitly. This makes the single-point join enforceable by DRC.
  2. Manual layout-only split approach: keep schematic GND as-is, manually delete/replace the current full-board GND fill with shaped copper regions and a documented bridge. This is faster but easier to accidentally violate because DRC still sees one logical GND net.
  3. Ignore split and bulk-autoroute: not recommended; this risks digital return through the analog region and shield/ground loop creation.
Current recommendation
Use option 1 before continuing: introduce explicit ground domains and a deliberate net-tie/0 Ω single-point join near U_LDO_A/U_REF. This is the only robust way to satisfy the Rev 2 grounding requirement during routing and manufacturing review.
  • Why routing stopped

  • Work completed before stopping

  • What is not complete

  • Required next decision

  • Current recommendation