Document Review and Assistance
Worked for 24 mins 43 sec
I’m blocked now because the account has no available ACUs, so I can’t run the final post-route DRC/airwire verification.
Accomplished this session:
- Ran pre-route validation: board was routable with 51 PCB components / 47 nets.
- Auto-routed the board, adding 880 routing nodes.
- Found post-route issues: 2 airwires and 4 overlapping-copper errors, localized mainly around C15 GND plus GND connectivity near U9/U5.
- Removed two conflicting trace segments and ran one cleanup auto-route pass, adding 9 routing nodes.
Open items:
- Final DRC/airwire check still needs to be run once ACUs are available.
- If errors remain, inspect C15 GND pad / bulk capacitor footprint area first.
- Low-noise analog routing should be visually reviewed before fabrication, especially sensor → LMP91000 → ADC paths and the 2.5 V reference routing.
Suggested next steps:
- Re-run full post-route DRC and airwire checks.
- Fix any remaining localized C15/GND overlap issues.
- Review analog/reference routing quality manually before generating manufacturing files.
Run final checks
Fix C15 GND
Review analog routing
Check ground returns
Checks and cleanup
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Ask about this doc
Board Bring-Up Plan — 4-Channel Gas Sensor AFE
Prerequisites
- Equipment: multimeter, oscilloscope, current-limited 3.3 V bench supply, logic analyzer or oscilloscope for I2C/SPI, external STM32F767ZI or compatible 3.3 V controller.
- Do not connect gas sensors until the 3.3 V and 2.5 V rails are verified.
- Treat the LMP91000 inputs and sensor headers as ESD-sensitive.
1. Visual Inspection
- Inspect U1–U4 LMP91000 devices, U5–U8 ADC devices, U9 voltage reference, J1 controller header, and J2–J5 sensor headers.
- Check for solder bridges on fine-pitch IC pins and headers.
- Confirm DNP-designated compensation/filter parts are populated only if intentionally required.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Measure At | Initial Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| 3V3 | External controller/header supply | 3.3 V | J1 3V3 pin or any U1–U4 VDD decoupling cap | 100 mA | 3.135–3.465 V, no overheating |
| VREF_2V5 | U9 LM4125AIM5-2.5 | 2.5 V | U9 VOUT / VREF_2V5 test point | Included in 3V3 limit | 2.45–2.55 V typical bring-up window |
| GND | Common board ground | 0 V reference | J1 GND / sensor header GND reference | N/A | Continuity across all GND points |
Procedure:
- With power off, measure resistance from 3V3 to GND and VREF_2V5 to GND; investigate any near-short.
- Apply 3.3 V with a 100 mA current limit and no sensors installed.
- Verify 3V3 at the LMP91000/ADC decoupling capacitors.
- Verify VREF_2V5 from U9.
- If current draw is abnormal, power down and inspect for shorts before continuing.
3. Digital Interface Verification
Table
| Interface | Nets | Components | Expected Behavior |
|---|---|---|---|
| I2C | I2C_SDA, I2C_SCL | J1, U1–U4, pull-ups R1/R2 | Idle high at 3.3 V; controller should detect LMP91000 addresses if address pins are correctly handled |
| SPI | SPI_SCLK, SPI_MISO, CH1_ADC_CS–CH4_ADC_CS | J1, U5–U8 | SCLK toggles during reads; only one chip-select active per ADC transaction; MISO returns ADC data |
Procedure:
- Verify I2C_SDA and I2C_SCL idle high before communication.
- Run an I2C scan from the controller and confirm the detected LMP91000 addresses match the final address configuration.
- Toggle each ADC chip select independently and observe activity at CH1_ADC_CS through CH4_ADC_CS.
- Read each ADC channel and confirm SPI_MISO changes during conversion/read cycles.
4. Analog Front-End Verification
Table
| Channel | AFE | Sensor Header | ADC Input Net | Checks |
|---|---|---|---|---|
| CH1 | U1 | J2 | CH1_ADC_IN | Verify CE/RE/WE header continuity and ADC input response |
| CH2 | U2 | J3 | CH2_ADC_IN | Verify CE/RE/WE header continuity and ADC input response |
| CH3 | U3 | J4 | CH3_ADC_IN | Verify CE/RE/WE header continuity and ADC input response |
| CH4 | U4 | J5 | CH4_ADC_IN | Verify CE/RE/WE header continuity and ADC input response |
Procedure:
- Keep sensors disconnected for the first electrical tests.
- Configure each LMP91000 over I2C according to the selected electrochemical sensor requirements.
- Verify VOUT/ADC input behavior with known safe test conditions before installing sensors.
- Install one sensor channel at a time and confirm stable readings before populating all four channels.
5. Functional Validation
Table
| Test | Expected Result | Pass Criteria |
|---|---|---|
| 3.3 V input only | Stable 3V3 and VREF_2V5 | Rails within limits and no abnormal current |
| I2C scan | LMP91000 channels detected/configurable | All intended channels respond |
| ADC SPI read | Each ADC selectable independently | Only selected channel drives valid data |
| Channel continuity | CE/RE/WE reach the correct LMP91000 pins | No shorts between electrodes |
| Sensor trial | One known-good sensor produces plausible output | Reading changes appropriately with controlled gas/test stimulus |
6. Known Bring-Up Risks
- ADS7866 is a placeholder/substitute for the intended ADC161S626 unless the design owner explicitly approves it.
- LMP91000 I2C addressing must be confirmed because the current library symbol did not expose ADDR0/ADDR1 pins.
- Final sensor-specific LMP91000 register values depend on the electrochemical sensor model and required bias/transimpedance settings.
Pass/Fail Summary
Table
| Section | Result | Notes |
|---|---|---|
| Visual inspection | [ ] Pass / [ ] Fail | |
| Power rails | [ ] Pass / [ ] Fail | |
| I2C interface | [ ] Pass / [ ] Fail | |
| SPI ADC interface | [ ] Pass / [ ] Fail | |
| Analog channel tests | [ ] Pass / [ ] Fail | |
| Sensor validation | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for layout/fabrication review / [ ] Requires schematic rework
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Digital Interface Verification
4. Analog Front-End Verification
5. Functional Validation
6. Known Bring-Up Risks
Pass/Fail Summary
