超声波信号采集与发射设计

当前实时检查发现 71 个 airwire、28 个重叠铜和 1 个悬空走线;我会先删除这些冲突/残留走线,再重新布线,否则直接布线会继续失败。
残留走线在多轮删除后仍持续暴露新的重叠点;我会改为按受影响网络清除旧路由,再重新布线这些网络,避免逐段删除反复产生残留。
阻塞项已清掉:当前只剩 airwire,未再看到重叠铜或悬空走线。我现在启动自动布线来消除空中电线。
已完成清理:重叠铜和悬空/残留走线已清除,当前主要剩余问题是 airwire。已启动自动布线,但额度用尽,任务暂停。
当前状态:
  • 已清掉多轮残留走线/重叠铜阻塞项。
  • 复查后进入自动布线前只剩 airwire。
  • 自动布线任务已启动但因额度不足暂停,任务 ID:auto-layout-249bbf96-74ec-46e3-abf4-b9b06aade4ab
下一步:补充额度后继续/重启自动布线,然后复查 ERC/DRC,目标把 airwire 清零。
定位 airwire
列出未布线网络
检查封装引脚
优化布线优先级
U1
C12
Capacitance
100nF
C20
Capacitance
100nF
C4
Capacitance
100nF
C27
Capacitance
10uF
C2
Capacitance
100nF
C21
Capacitance
100nF
C24
Capacitance
100nF
C26
Capacitance
1uF
C5
Capacitance
100nF
C22
Capacitance
100nF
C3
Capacitance
100nF
C13
Capacitance
10nF
C30
Capacitance
100nF
C18
Capacitance
100nF
C14
Capacitance
100nF
C29
Capacitance
100nF
C8
Capacitance
2.2uF
C28
Capacitance
10uF
C1
Capacitance
100nF
C31
Capacitance
100nF
C19
Capacitance
100nF
C16
Capacitance
100nF
C7
Capacitance
2.2uF
C10
Capacitance
10uF
C6
Capacitance
100nF
C11
Capacitance
100nF
C9
Capacitance
100nF
C17
Capacitance
100nF
C23
Capacitance
100nF
C25
Capacitance
1uF
U1 PD0 - U3 CONVST_A
U8 IN1- - R6 P2
U4 VO - U7 IN_A
L1 P2 - U1 VDDA
U1 PA4 - U2 ~FSYNC
U1 VCAP_1 - C7 P1
J2 1 - U1 VDD
U1 VCAP_2 - C8 P1
U1 VCAP_2 - C8 P1
U1 VREF+ - U2 VDD
U1 PB15 - U3 DB8/DOUT_B
U1 PA7 - U2 SDATA
U3 V1 - R5 P2
U7 OUT_B - J9 2
J7 1 - U3 AVCC
U3 AVCC - U8 V+
U1 PD2 - U3 RESET
U1 PA13 - J6 Pin_3
U5 VDD11 - U6 VDD2
U6 VDD11 - U7 VDD
U4 VDD11 - U5 VDD11
U5 VDD11 - U6 VDD2
U3 V8GND - U8 V-
U1 VCAP_1 - C7 P1
HV_PZT_OUT_P_1000VPK
U3 AVCC - U8 V+
U1 PA13 - J6 Pin_3
U1 VREF+ - U2 VDD
U5 GND22 - U6 GND1
U2 VOUT - R3 P1
J7 2 - U3 AGND
U1 PA8 - U2 MCLK
R4 P2 - D1 A
U3 V1 - R5 P2
R4 P2 - D1 A
U3 V8GND - U8 V-
U1 PA7 - U2 SDATA
J3 1 - U4 VDD2
U3 REFIN/REFOUT - C27 P1
U3 V8GND - U8 V-
U3 V8GND - U8 V-
U3 V8GND - U8 V-
U3 V8GND - U8 V-
U5 VDD11 - U6 VDD2
J3 1 - U4 VDD2
U2 COMP - C13 P1
U5 VDD11 - U6 VDD2
U1 PA10 - J6 Pin_6
U4 VDD11 - U5 VDD11
U3 V8GND - U8 V-
L1 P2 - U1 VDDA
U5 GND22 - U6 GND1
J3 2 - U4 GND22
U6 VDD11 - U7 VDD
U1 PA5 - U2 SCLK
U3 REFGND - U3 V1GND
U7 OUT_B - J9 2
U3 AVCC - U8 V+
U1 NRST - R2 P1
U1 PA4 - U2 ~FSYNC
U3 V8GND - U8 V-
J3 1 - U4 VDD2
U1 PA9 - J6 Pin_5
U3 REFGND - U3 V1GND
U3 V8GND - U8 V-
U3 V8GND - U8 V-
U6 VO - U1 PD5
U5 VDD11 - U6 VDD2
U3 REFIN/REFOUT - C27 P1
R4 P2 - D1 A
J3 2 - U4 GND22
U5 VDD11 - U6 VDD2
U1 PB14 - U3 DB7/DOUT_A
U6 VI - R7 P1
R3 P2 - J8 Pin_1
J7 2 - U3 AGND
U4 VO - U7 IN_A
U1 PD4 - U5 VI
J7 1 - U3 AVCC
U3 V8GND - U8 V-
U1 VREF+ - U2 VDD
AC_L_EXT
U3 REGCAP - C26 P1
U5 GND22 - U6 GND1
L1 P2 - U1 VDDA
HV_PZT_OUT_N_1000VPK
U1 PA14 - J6 Pin_4
U1 PA10 - J6 Pin_6
U8 IN1- - R6 P2
U4 GND22 - U5 GND22
U3 AVCC - U8 V+
U3 AVCC - U8 V+
U3 V8GND - U8 V-
U5 VDD11 - U6 VDD2
U3 V8GND - U8 V-
U1 NRST - R2 P1
U4 GND22 - U5 GND22
U1 PD2 - U3 RESET
U3 REGCAP - C25 P1
U3 REFCAPB - C28 P1
R4 P2 - D1 A
U3 V8GND - U8 V-
U3 V8GND - U8 V-
U3 AVCC - U8 V+
U1 PA5 - U2 SCLK
U5 VDD11 - U6 VDD2
U5 VDD11 - U6 VDD2
J2 1 - U1 VDD
U1 PD3 - U4 VI
U1 PB15 - U3 DB8/DOUT_B
U6 VO - U1 PD5
U5 VO - U7 IN_B
U6 VDD11 - U7 VDD
U3 REGCAP - C25 P1
U3 V8GND - U8 V-
U3 V8GND - U8 V-
U5 VDD11 - U6 VDD2
AC_N_EXT
U5 GND22 - U6 GND1
U7 OUT_A - J9 1
J5 Pin_1 - R4 P1
U2 CAP/2.5V - C11 P1
U1 PB12 - U3 ~CS
U3 V8GND - U8 V-
U1 PD1 - U3 BUSY
U3 V8GND - U8 V-
U5 VDD11 - U6 VDD2
U5 VO - U7 IN_B
U3 AVCC - U8 V+
J3 1 - U4 VDD2
U1 NRST - R2 P1
J2 1 - U1 VDD
U1 BOOT0 - R1 P1
U1 BOOT0 - R1 P1
U1 PA14 - J6 Pin_4
R4 P2 - D1 A
J7 1 - U3 AVCC
U5 GND22 - U6 GND1
U2 VOUT - R3 P1
U3 AVCC - U8 V+
J5 Pin_1 - R4 P1
U3 V8GND - U8 V-
U5 VDD11 - U6 VDD2
U2 CAP/2.5V - C11 P1
U3 REGCAP - C26 P1
U6 VDD11 - U7 VDD
U1 NRST - R2 P1
U1 PA8 - U2 MCLK
U1 PB13 - U3 ~RD~/SCLK
U5 VDD11 - U6 VDD2
J3 2 - U4 GND22
U1 PB12 - U3 ~CS
U1 PB13 - U3 ~RD~/SCLK
U5 VDD11 - U6 VDD2
U2 COMP - C13 P1
U1 PD3 - U4 VI
U5 GND22 - U6 GND1
U1 PD0 - U3 CONVST_A
U1 PB14 - U3 DB7/DOUT_A
U3 V8GND - U8 V-
U3 REFCAPB - C28 P1
U1 PA9 - J6 Pin_5
U1 PD1 - U3 BUSY
U6 VI - R7 P1
U6 VDD11 - U7 VDD
J2 1 - U1 VDD
U1 PD4 - U5 VI
U7 OUT_A - J9 1
R3 P2 - J8 Pin_1
U5 VDD11 - U6 VDD2
U3 V8GND - U8 V-
U1 VSS - U2 DGND
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
GND
GND
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U1 VSS - U2 DGND
GND
U6 GND22 - C1 P2
GND
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U1 VSS - U2 DGND
U1 VSS - U2 DGND
U6 GND22 - C1 P2
U3 OS2 - U3 DB15/BYTE_SEL
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U6 GND22 - C1 P2
U1 VSS - U2 DGND
U3 OS2 - U3 DB15/BYTE_SEL
R1
Resistance
10kΩ
J9
J6
D2
J7
D1
J4
U5
R4
Resistance
1kΩ
U2
J8
J2
U6
R5
Resistance
100Ω
R7
Resistance
10kΩ
U4
R3
Resistance
200Ω
J3
J1
J5
R2
Resistance
10kΩ
R6
Resistance
1MΩ
U8
L1
Inductance
100Ω@100MHz ferrite bead placeholder H
U7
U3

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Firmware Starter — STM32F407VGT6
Platform and toolchain
  • MCU: STM32F407VGT6
  • Recommended framework: STM32 HAL
  • Build system: STM32CubeIDE or PlatformIO with STM32Cube framework
  • Clock assumption: configure HSE/PLL or HSI/PLL to a stable system clock; configure PA8 as MCO or timer/PWM clock output for the AD9833 MCLK requirement.
Schematic pin mapping

Table


FunctionMCU pinNetDirectionNotes
AD9833 SCLKPA5DDS_SPI_SCLKOutputSPI clock to U2 SCLK
AD9833 SDATAPA7DDS_SPI_MOSIOutputSPI MOSI to U2 SDATA
AD9833 FSYNCPA4DDS_SPI_CSOutputActive-low frame sync
AD9833 MCLKPA8DDS_MCLKOutputUse MCO or timer clock; AD9833 output frequency depends on this clock
AD7606 SCLKPB13ADC_SPI_SCLKOutputSPI clock to U3 RD/SCLK
AD7606 CSPB12ADC_SPI_CSOutputActive-low ADC chip select
AD7606 DOUTAPB14ADC_DOUTAInputSPI data input
AD7606 DOUTBPB15ADC_DOUTBInputOptional second serial data lane
AD7606 CONVSTPD0ADC_CONVSTOutputDrives CONVST_A and CONVST_B together for simultaneous sampling
AD7606 BUSYPD1ADC_BUSYInputConversion busy flag
AD7606 RESETPD2ADC_RESETOutputReset pulse after power-up
TX triggerPD3TX_TRIGGEROutputIsolated through U4
TX blankingPD4TX_BLANKINGOutputIsolated through U5
HV statusPD5HV_STATUSInputIsolated feedback through U6
SWDIOPA13SWDIODebugJ6
SWCLKPA14SWCLKDebugJ6
UART TXPA9UART_TXOutputJ6 debug UART
UART RXPA10UART_RXInputJ6 debug UART
ResetNRSTMCU_RSTInputJ6 reset + pull-up/filter
Boot modeBOOT0BOOT0StrapPulled down for normal boot
Bring-up sequence
  1. Initialize clocks and GPIO.
  2. Assert AD7606 RESET pulse.
  3. Configure AD9833 over SPI for sine output at 500kHz.
  4. Arm acquisition timer for PRF = 100Hz.
  5. On each 10ms period:
    • Start capture window.
    • Output TX trigger/blanking timing.
    • Generate or gate the five-cycle 10us burst.
    • Pulse AD7606 CONVST and read samples after BUSY falls.
  6. Keep HV output disabled unless external interlocks and isolated power-good are valid.
Minimal STM32 HAL skeleton

C


#include "stm32f4xx_hal.h"
#include <stdint.h>

#define DDS_CS_PORT      GPIOA
#define DDS_CS_PIN       GPIO_PIN_4
#define DDS_MCLK_PORT    GPIOA
#define DDS_MCLK_PIN     GPIO_PIN_8

#define ADC_CS_PORT      GPIOB
#define ADC_CS_PIN       GPIO_PIN_12
#define ADC_BUSY_PORT    GPIOD
#define ADC_BUSY_PIN     GPIO_PIN_1
#define ADC_CONVST_PORT  GPIOD
#define ADC_CONVST_PIN   GPIO_PIN_0
#define ADC_RESET_PORT   GPIOD
#define ADC_RESET_PIN    GPIO_PIN_2

#define TX_TRIG_PORT     GPIOD
#define TX_TRIG_PIN      GPIO_PIN_3
#define TX_BLANK_PORT    GPIOD
#define TX_BLANK_PIN     GPIO_PIN_4
#define HV_STATUS_PORT   GPIOD
#define HV_STATUS_PIN    GPIO_PIN_5

SPI_HandleTypeDef hspi1; // AD9833 on PA5/PA7, software CS PA4
SPI_HandleTypeDef hspi2; // AD7606 on PB13/PB14/PB15, software CS PB12
TIM_HandleTypeDef htim_prf;

static void dds_write16(uint16_t word) {
    uint8_t tx[2] = { (uint8_t)(word >> 8), (uint8_t)(word & 0xFF) };
    HAL_GPIO_WritePin(DDS_CS_PORT, DDS_CS_PIN, GPIO_PIN_RESET);
    HAL_SPI_Transmit(&hspi1, tx, 2, HAL_MAX_DELAY);
    HAL_GPIO_WritePin(DDS_CS_PORT, DDS_CS_PIN, GPIO_PIN_SET);
}

static void ad9833_set_sine_500khz(uint32_t mclk_hz) {
    // AD9833 frequency word = fout * 2^28 / MCLK.
    uint32_t fw = (uint32_t)(((uint64_t)500000UL * 268435456ULL) / mclk_hz);
    dds_write16(0x2100); // reset + write frequency registers
    dds_write16(0x4000 | (fw & 0x3FFF));
    dds_write16(0x4000 | ((fw >> 14) & 0x3FFF));
    dds_write16(0xC000); // phase 0
    dds_write16(0x2000); // exit reset, sine output
}

static void ad7606_reset(void) {
    HAL_GPIO_WritePin(ADC_RESET_PORT, ADC_RESET_PIN, GPIO_PIN_SET);
    HAL_Delay(1);
    HAL_GPIO_WritePin(ADC_RESET_PORT, ADC_RESET_PIN, GPIO_PIN_RESET);
}

static void ad7606_start_conversion(void) {
    HAL_GPIO_WritePin(ADC_CONVST_PORT, ADC_CONVST_PIN, GPIO_PIN_SET);
    for (volatile int i = 0; i < 20; ++i) { __NOP(); }
    HAL_GPIO_WritePin(ADC_CONVST_PORT, ADC_CONVST_PIN, GPIO_PIN_RESET);
}

static void ad7606_read_two_lanes(uint16_t *douta, uint16_t *doutb, uint8_t count) {
    // For two-lane serial mode, 64 SCLK cycles read all 8 channels.
    // This placeholder uses SPI2 RX; exact dual-lane capture may need DMA or GPIO sampling for DOUTB.
    uint8_t rx[16] = {0};
    HAL_GPIO_WritePin(ADC_CS_PORT, ADC_CS_PIN, GPIO_PIN_RESET);
    HAL_SPI_Receive(&hspi2, rx, count * 2, HAL_MAX_DELAY);
    HAL_GPIO_WritePin(ADC_CS_PORT, ADC_CS_PIN, GPIO_PIN_SET);
    for (uint8_t i = 0; i < count; ++i) {
        douta[i] = ((uint16_t)rx[2*i] << 8) | rx[2*i + 1];
    }
    (void)doutb;
}

static void fire_burst_window(void) {
    HAL_GPIO_WritePin(TX_BLANK_PORT, TX_BLANK_PIN, GPIO_PIN_SET);
    HAL_GPIO_WritePin(TX_TRIG_PORT, TX_TRIG_PIN, GPIO_PIN_SET);
    // 500kHz five-cycle burst is 10us. Use a hardware timer in production.
    for (volatile int i = 0; i < 1000; ++i) { __NOP(); }
    HAL_GPIO_WritePin(TX_TRIG_PORT, TX_TRIG_PIN, GPIO_PIN_RESET);
    HAL_GPIO_WritePin(TX_BLANK_PORT, TX_BLANK_PIN, GPIO_PIN_RESET);
}

int main(void) {
    HAL_Init();
    SystemClock_Config();
    MX_GPIO_Init();
    MX_SPI1_Init();
    MX_SPI2_Init();
    MX_TIM_Init();

    HAL_GPIO_WritePin(DDS_CS_PORT, DDS_CS_PIN, GPIO_PIN_SET);
    HAL_GPIO_WritePin(ADC_CS_PORT, ADC_CS_PIN, GPIO_PIN_SET);
    HAL_GPIO_WritePin(TX_TRIG_PORT, TX_TRIG_PIN, GPIO_PIN_RESET);
    HAL_GPIO_WritePin(TX_BLANK_PORT, TX_BLANK_PIN, GPIO_PIN_RESET);

    ad7606_reset();
    ad9833_set_sine_500khz(25000000UL); // update if actual MCLK differs

    while (1) {
        if (HAL_GPIO_ReadPin(HV_STATUS_PORT, HV_STATUS_PIN) == GPIO_PIN_SET) {
            fire_burst_window();
        }
        ad7606_start_conversion();
        while (HAL_GPIO_ReadPin(ADC_BUSY_PORT, ADC_BUSY_PIN) == GPIO_PIN_SET) {}
        uint16_t samples_a[8], samples_b[8];
        ad7606_read_two_lanes(samples_a, samples_b, 8);
        HAL_Delay(10); // 100Hz PRF placeholder; replace with hardware timer for deterministic timing
    }
}
Notes
  • The 10us burst timing and 100Hz PRF should be implemented with hardware timers, not delay loops, in production firmware.
  • The Hamming window requires amplitude gating or DAC/amplifier control in the external HV module; if the external HV module only accepts trigger pulses, firmware can only time the burst, not shape the analog amplitude.
  • Verify actual AD9833 MCLK frequency before calculating the frequency word.
  • Verify AD7606 serial read mode in firmware against the final selected single-lane or dual-lane read strategy.
  • Platform and toolchain

  • Schematic pin mapping

  • Bring-up sequence

  • Minimal STM32 HAL skeleton

  • Notes

1kV 超声波脉冲发射与同步采集装置 thumbnail
220VAC 输入、隔离式 1kV 超声波瞬态发射与同步采集系统,支持 0–1MHz 五周期汉明窗正弦突发波形。

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