Completed the explicitly requested FC envelope change from 160 × 100 mm to 39 × 39 mm, sharp-corner rectangle, centered at the origin (edges ±19.5 mm). This is a prototype envelope, not reproduction of original side-open notches. No mounting holes, zones, routing, independent component moves, rotations or side changes were performed. Separate ESC project untouched.

Fresh layout summary confirms sizeX=39mm, sizeY=39mm, rectangle, four copper layers, 80 components and 69 nets. Manufacturing target read before and after is unchanged: Standard Density (SDI) v3, applied, and JLCPCB SDI 4 Layer v1, applied. No manufacturing rules or stackup mutation was requested. Existing minimum trace width 0.127 mm, through-via drill 0.25 mm and diameter 0.55 mm preserved; do not loosen these for fit.

Tool behavior noteworthy: resizing automatically changed reported component coordinates by the same translation (+60.5 mm X, +30.5 mm Y). The relative arrangement, rotations and Top side were unchanged. No placement API was invoked. Existing component bounding-box size remains 143.16 × 157.59 mm, so this is sizing only, not a placed board.

Read footprint-bound area is 1061 mm². Board area is 1521 mm²; estimated one-side occupancy 69.8% (tool displays 69.7% from unrounded area). This excludes screw hardware, cable bodies, courtyards and routing channels. Tool routing-aware area with a generic 1 mm allowance per component side is 2379 mm², or 156.4% of board area. This is a warning proxy, not proof of failure or routeability; its automatic 'all fit' and 'routing looks fine' messages must not be read as verified placement.

A 30.5 mm square centered mount pattern has candidate centers (±15.25, ±15.25) mm, 4.25 mm from each nearest edge. A plain Ø4 mm circle at these centers would retain 2.25 mm of material to the edge: it is not side-open. Opening direction, neck width, washer/grommet dimensions, positional tolerances and original notch contour remain unknown.

PROVISIONAL planning reservations only: keep radius 3 mm around each candidate center on both component sides and all copper layers, and leave its nearest outward corner sector clear. This is an estimated planning clearance, not a hardware-qualified keepout or invented cutting profile. No such reservations have been added as CAD nodes. Four radius-3 discs consume about 113 mm²; with these nominal reservations the one-side occupancy rises to approximately 75.4%. Enlarge the reservation if actual washers/grommets demand it.

Bottom small passives are recommended, and should be treated as necessary planning allowance for this density rather than claiming single-side fit. Existing resistor/capacitor bounds total approximately 160 mm²; moving all of them still leaves about 59% of the gross top area occupied. Bottom passives alone therefore do not guarantee fit. Allow a later separately approved bottom flash/ESD fallback if top-side compaction fails; no part replacement or board-size change is implied.

All 80 current components are on Top, with 0° element rotation in the read. No placement-lock rule/property was exposed in the complete element/ruleset and component-property survey. This is 'no lock observed', not a guarantee of an unexposed UI lock. No dedicated mounting-hole components or zone nodes were found; the two circle primitives in the node summary are not evidence of mounting holes. Existing manufacturing clearance rules are preserved.

Header evidence: 61300611121 is vertical, not right-angle; exposed mating pins are 6 ±0.2 mm above the insulator, and PCB tails are 3 ±0.2 mm below it. Exact PCB-surface-to-tip height was not explicitly established by the query. Insulator-height answer 2.54 ±0.2 mm failed claim validation and is unverified, so do not use a computed 8.54 mm as a certified height. The exposed pin length alone exceeds the 4.9 mm reference assembly height: the existing header prototype cannot be represented as reproducing that height. Cable/socket bodies further increase height and may obstruct adjacent rows.

Every footprint has a model node, but computed packageSize is {0,0,0}, with no reliable assembly-height or mating-axis field in the survey. Model offsets (e.g. header Z=2 mm) are transforms, not package heights. Mating directions above come from manufacturer evidence, not guessed 3D orientation. Exact physical pin-1 orientation and connector edge datum must be checked before actual anchor placement.

Other large bounds: U1 MCU 13.90 × 13.31 mm; U2 IMU 7.74 × 3.00; U3 flash 9.35 × 5.88; F2 7.37 × 4.44; D8 7.04 × 3.63. These are tool/layout bounds, not certified package-body dimensions; F2 and IMU in particular deserve a pad/courtyard audit before judging compaction. There are no LEDs, switches, buzzer, radio antenna or display in this inventory.

Coordinate convention is top view, north=+Y, east=+X; all connector bodies remain Top. Header centers below are planning centers of their bound boxes, not footprint-origin commands. All header long axes run parallel to the corresponding edge, with vertical +Z mating rather than side insertion.

Each 16.04 mm row is centered between provisional corner reservations; body bounds alone clear those reservations. Two such rows end-to-end on one edge would need 32.08 mm before gaps, but the span between radius-3 mount reservations is only 24.5 mm, hence the proposed parallel inner/outer rows. Approximately 5 mm row spacing is a starting layout allowance, not verified for mated sockets; approval must cover the actual cable/socket size and access. If bulky sockets do not fit, hold placement and ask for a revised interface strategy; do not silently swap connectors.

These are a full-board approval proposal, not exact placement coordinates or a fit proof. Mount hardware, mated socket dimensions, USB edge datum, Bottom permission and acceptable prototype height must be settled by the lead before placement.