Draft design for a compact per-locomotive module that accepts 18 VAC from track pickups, rectifies it to a ~24 V DC bus, and regenerates a 5 A bipolar DCC waveform for a stock DCC/MTH decoder. The design uses an assembler-friendly ESP32-WROOM-32UE module instead of a bare Espressif chip.
Intended Use
Installed inside an O-scale locomotive/tender. Prototype-to-small-build design intended for standard PCB fabrication and assembly.
What the Device Should Do
Take 18 VAC from locomotive track pickups.
Generate a bipolar DCC output to a decoder at up to 5 A.
Connect over WiFi to JMRI/WiThrottle and synthesize DCC timing in firmware.
Monitor H-bridge fault and current-sense signals for overload shutdown.
Provide an external USB-UART programming/debug header.
Main Features
18 VAC input through inline 6 A PTC protection.
Discrete SS510 Schottky bridge rectifier.
VBUS transient protection with SMBJ26A TVS.
DRV8873 H-bridge output stage.
ESP32-WROOM-32UE WiFi/Bluetooth module with u.FL antenna connection.
3.3 V buck regulator from VBUS.
JST-VH high-current input/output connectors.
System Architecture
Diagram
Power Tree and Power Budget
18 VAC input, nominal rectified peak about 25 V.
DCC output design target: 5 A intermittent/decoder load.
3.3 V rail loads: ESP32 WiFi module, 74LVC1G04, DRV8873 logic. Provisional regulator target: >=600 mA peak.
Open thermal item: DRV8873 continuous 5 A copper/thermal validation.
Manufacturing and Assembly Expectations
Use real library parts with standard assembler-compatible footprints.
Avoid bare Espressif chip/RF design; use ESP32-WROOM-32UE certified module with onboard u.FL.
Prefer SMD passives/power semiconductors except JST-VH and programming header.
Target board size from source spec: about 30 mm x 24 mm, subject to thermal copper area.
Firmware-Relevant Hardware Requirements
ESP32 GPIO25 outputs DCC signal via RMT.
Complementary signal generated through 74LVC1G04 inverter.
ESP32 controls DRV8873 enable/sleep, reads nFAULT, and samples IPROPI current sense by ADC.
Programming header exposes 3V3, GND, TX, RX, EN, and IO0.
Physical Design Expectations
Compact two-layer PCB unless thermal/EMI review requires more copper or layers.
ESP32-WROOM-32UE u.FL antenna must route to an external antenna suitable for metal locomotive shells.
DRV8873 PowerPAD requires large copper pour and thermal vias if available.
Important Design Decisions
Use ESP32-WROOM-32UE module rather than a bare Espressif chip because PCBWay rejected bare Espressif assembly and module RF assembly/certification is safer.
Use DRV8873 single H-bridge instead of discrete FET gate-driver bridge for compactness and protection.
Use a high-voltage buck regulator for 3.3 V instead of an LDO due to VBUS near 24 V.
Assumptions
Transformer nominal is 18 VAC and decoder tolerates DCC amplitude in the expected VBUS range.
5 A is intermittent/peak; continuous thermal performance must be bench-verified.
External USB-UART adapter provides 3.3 V logic only, not 5 V UART.
Change Notes
Initial project file created from attached DCC-module-design.md.