Project Idea Started

flux

The runnable portal package is already available today; hardware work is now underway block-by-block. I’m prioritizing safe power distribution and the STM32/USB path first because those determine whether the carrier can become a usable bench prototype.

flux

The usable software POC is ready today: download WarzaTools Studio Portal v7. It includes Windows and Steam Deck/Linux launchers, the unified sidebar portal, WarzaTV integration, device simulation, program registry, plug-in SDK, Flatpak architecture, and the safe console/firmware framework.
A full schematic-completion pass was also dispatched and finished, covering power, STM32H742, USB roles, controller interfaces, networking, video/UI headers, and debug/security. However, I was unable to retrieve and independently review its report, inspect the resulting net count, run the required final ERC remediation, or export a revised hardware handoff. Therefore, the PCB must still be treated as unverified and not fabrication-ready.
Remaining hardware work
  • Inspect the completed schematic mutations and confirm all new nets.
  • Independently verify every active IC against its datasheet.
  • Run ERC and correct critical connectivity issues.
  • Confirm the unresolved x86/display/capture power requirements.
  • Freeze connector and module pinouts.
  • Export updated PDF, EDIF, BOM, and ZIP.
  • Only then begin PCB placement and routing.
Execution stopped because your ACUs ran out.
"WarzaTools Schematic Build" completed.

flux

The software POC remains the usable deliverable today: download WarzaTools Studio Portal v7.
The hardware carrier was partially advanced: power-entry, regulation, USB-C control, USB power switching, USB mux/PHY, Ethernet connector, HDMI connector, SWD header, and secure-element nets were created. However, this is not yet a usable or fabrication-ready prototype: the STM32 core rails/decoupling and most signal buses remain unwired, several placeholder passives still need values, and ERC/layout/routing/export validation is unfinished.
Execution stopped because your ACUs ran out.
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Files

Schematic

Layout

3D View

Design Notes
Phase-1 Scope Boundary
This revision is an integration and measurement carrier, not a final handheld motherboard. It deliberately avoids committing to an x86 CPU/DDR implementation, direct HDMI receiver silicon, battery pack, display panel, antenna geometry, or console-specific authentication hardware before compatibility and thermal benchmarks exist.
Electrical Strategy
  • Use a protected 12 V bench input and a replaceable high-current 5 V DC/DC module interface.
  • Generate 3.3 V locally for deterministic-control logic.
  • Switch and monitor each exposed USB VBUS branch independently.
  • Keep USB 2.0 differential paths short and controlled; route USB 3/HDMI through proven modules/cables in this revision.
  • Provide internal USB plus UART recovery between Linux and MCU.
  • Expose latency timestamp GPIO and all fault/enable signals.
Handoff Expectations
The first deliverable is a readable, functionally grouped schematic and BOM suitable for continued manual refinement. A fabrication-ready Gerber package is only appropriate after exact SBC, capture, Ethernet, connector, board-outline, and mechanical choices are frozen and PCB placement/routing are completed.

  • Phase-1 Scope Boundary

  • Electrical Strategy

  • Handoff Expectations