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Project Specification — Vitachrona Main Watch PCB
Project Overview
Status: RK3568 migration authorized and staged non-destructively as U30/U31; destructive implementation remains BLOCKED by DDR library quality, exact topology, power and connector gates.
Production-intent medical wearable main board with Linux-class compute, LTE/GNSS, BLE hub, NFC, sensing, wireless charging and harvesting in a preserved 98 mm circular envelope.
Hard retained subsystems
Exactly retain ST4SIM-300M, nRF5340 hub, PN7160, Qi/BQ25895, harvesting interfaces, AD5940, main-board sensors, eMMC, BG95M3LA-64-SGNS and the 40-pin MIPI display interface. BG95 debug remains on an independent native USB2 path.
Authoritative compute direction
- RK3568, Flux UID
111e7434-7f63-4f64-9fe8-9ab643a6378e. - RK809-5 direction, UID
eeac72e7-5a15-422a-9419-94a00f7c7455. - U30 RK3568 and U31 RK809-5 are present in the
RK3568 Migration StagingFunctional Group. They are intentionally not connected to provisional rails/signals until the source-backed DDR and PMIC maps close. - x32 LPDDR4/LPDDR4X 200-ball topology. Samsung K4F6E3S4HM-MGCJ is audited as an LPDDR4 candidate but is not releaseable because its library terminal types are unspecified and complete coordinate/topology reconciliation remains open.
- Retain MTFC16GAPALBH-IT eMMC after current/pin audit closure.
Dock architecture
The board now includes staged custom component J30 / VITACHRONA-DOCK-USB3X-16, a keyed 16-contact watch-side target-pad interface. This is a bespoke interface and not a USB connector standards claim. Contact order, left-to-right when viewing the watch PCB Top face with the asymmetric key holes below the contact row, is:
Table
| Pin | Function | Pin | Function |
|---|---|---|---|
| 1 | SHIELD_A | 9 | USB2_DP |
| 2 | GND_TX_A | 10 | USB2_DM |
| 3 | SSTX_P | 11 | GND_PWR |
| 4 | SSTX_N | 12 | VBUS_A |
| 5 | GND_TX_RX | 13 | VBUS_B |
| 6 | SSRX_P | 14 | DOCK_DETECT |
| 7 | SSRX_N | 15 | DOCK_ID |
| 8 | GND_RX_USB2 | 16 | SHIELD_B |
Electrical allocation carries:
- VBUS
- At least two ground/return contacts
- USB2 D+/D- connected to the RK3568 OTG device path for Rockusb/Maskrom recovery/programming
- USB3 SSTX+/-, SSRX+/- for normal data
- Dock detect/orientation/keying contact where applicable
No exact suitable built-in connector was available. The sourced technology direction is a Johoty custom impedance-controlled high-speed pogo module: the manufacturer advertises >10 Gbps designs, DC-to-10 GHz customization, 1–2 A standard contacts, <=20 mOhm initial contact resistance, and custom 50/90/100-ohm structures. Mill-Max guidance supports spring travel, pad mating, alignment tolerance and multi-cycle durability but does not itself establish USB 3.x bandwidth; Smiths Interconnect is a qualified alternate custom spring-probe supplier for blind-mate/high-frequency mixed-signal assemblies.
J30 footprint datum is the center of the 16-land Top-face row. Lands are at 1.0 mm pitch from x=-7.5 to +7.5 mm; USB signal lands are 0.55 x 1.40 mm, grounds 0.60 x 1.60 mm, VBUS 0.75 x 1.80 mm, and shields 0.70 x 1.80 mm. Two unbound NPTH features key and retain the dock: round 1.2 mm hole at (-6.0,-2.5) mm and oblong 2.0 x 1.2 mm slot at (+6.5,-2.5) mm. Dock probes approach normal to the PCB Top face; the asymmetric round/slot pattern prevents 180-degree reversal. Gold finish, solder-mask opening, probe crown, working stroke, force, housing datums and enclosure retention remain vendor/prototype deliverables.
USB requirements:
- Dock USB2: 90 ohm differential.
- Dock USB3 TX/RX: 85 ohm differential.
- Low-capacitance SuperSpeed ESD candidate: TPD4EUSB30; addition waits for real endpoints to avoid orphan nets.
- VBUS protection/load switch waits for confirmed source role/current/inrush contract.
- VBUS_A and VBUS_B are paralleled on
DOCK_VBUS_5V; architecture limit is provisionally 2 A total (1 A/contact) until the selected custom module is thermally/current validated. - USB3 TX AC coupling must follow the final authoritative RK3568 reference topology.
- BG95 native USB2 debug remains independent and 90 ohm differential.
IOMUX/VCCIO release rule
Dedicated RK3568 eMMC, USB and DSI balls are identified, but retained low-speed assignments are not wired until a complete authoritative IOMUX/VCCIO table proves each bank voltage and alternate function.
FLASH_VOL_SEL must match VCCIO2 (3.3 V low, 1.8 V high).Non-destructive migration rule
Do not remove the preserved legacy compute, FlexSPI/NOR/PSRAM, FT600/SuperSpeed or SARA-substitution circuitry until the RK3568/RK809/DRAM/eMMC block passes part audits, is staged with source-backed power/clocks/reset/boot/DRAM/eMMC/decoupling, retained interfaces are reconnected, and ERC validates replacement connectivity.
Physical implementation
- Preserve 98 mm circular board boundary.
- Stackup is now an 8-copper-layer electrical plan: signal / GND / signal / power / GND / signal / GND / signal.
- Final fabrication requires approved HDI build-up, laser microvias, sequential lamination, filled/capped via-in-pad, and field-solver/coupon-derived DDR/USB/MIPI geometries.
- No routing is authorized yet.
- Schematic net metadata now declares dock and BG95 USB2 pairs as 90-ohm differential and dock USB3 TX/RX as 85-ohm differential. Final widths/gaps require a fabricator field solver and coupons.
Current audit and ERC evidence
- RK3568: 636 terminals/636 pads; source package 19 x 19 mm, 0.65 mm; full coordinate audit incomplete.
- RK809-5: 69 terminals/69 pads; QFN68 7 x 7 mm, 0.35 mm, grounded EP; exact rail/OTP mapping incomplete.
- Samsung LPDDR4: 200 terminals/200 pads; 10 x 15 mm mixed 0.65/0.80 mm grid; terminal typing fails release gate.
- Chosen migration-memory direction remains Samsung K4F6E3S4HM-MGCJ LPDDR4 x32; it is selected for the migration plan but not layout/release qualified until terminal typing and the complete RK3568 ball/topology cross-table close.
- J30 custom dock: 16 terminals; 16 distinct Top copper lands plus 2 asymmetric NPTH key/mount features. It is staged and schematically connected to RK3568 OTG USB2/USB3, ID, detect, VBUS-detect, GND and SHIELD nets; PCB placement/routing is intentionally not performed.
- Fresh pre-change ERC: 755 = 619 floating + 105 missing-power + 31 single-pin nets.
- Post-staging checks were rerun. The project remains unreleased with extensive pre-existing ERC/DRC findings; U30/U31 are intentionally isolated staging components, not a claimed functional core.
Release criteria
- Complete core terminal/ball/pad coordinate audits against authoritative drawings.
- Correctly typed, exact DRAM library part and source-backed RK3568 LPDDR topology.
- Exact RK809-5 rail map, sequencing and support components with closed current/headroom budget.
- Authoritative retained-interface IOMUX/VCCIO allocation.
- Verified keyed 12-contact dock connector and VBUS contract.
- Replacement core staged and ERC-validated before legacy deletion.
- Final HDI stackup and impedance geometry approved by fabricator/field solver before routing.
- Build and measure mating prototypes: contact-force/overtravel/tolerance stack, VBUS temperature rise and droop, TDR/S-parameters, USB eye/BER, ESD and USB compliance. J30 must not be called production-qualified before these pass.
Project Overview
Hard retained subsystems
Authoritative compute direction
Dock architecture
IOMUX/VCCIO release rule
Non-destructive migration rule
Physical implementation
Current audit and ERC evidence
Release criteria
