# [2-layer] JLCPCB Constraints rzDr ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** vishnu007 - **Created:** 12/16/2024 - **Last Updated:** 12/16/2024 - **Visibility:** Public ## Key Components ### U1 — [TM4C1294KCPDTT3](https://www.flux.ai/adrian95/tm4c1294kcpdtt3~a55.md) - Datasheet URL: https://www.ti.com/lit/ds/symlink/tm4c1294kcpdt.pdf - License: https://creativecommons.org/licenses/by/4.0/ - Part Type: Microcontroller - Manufacturer Name: Texas Instruments - Manufacturer Part Number: TM4C1294KCPDTT3 **Pins:** - ~HIB [pin 65] - ~RST [pin 70] - ~WAKE [pin 64] - EN0RXIN [pin 53] - EN0RXIP [pin 54] - EN0TXON [pin 56] - EN0TXOP [pin 57] - GND_1 [pin 17] - GND_2 [pin 48] - GND_3 [pin 55] - GND_4 [pin 58] - GND_5 [pin 80] - GND_6 [pin 114] - GNDA [pin 10] - OSC0 [pin 88] - OSC1 [pin 89] - PA0 [pin 33] - PA1 [pin 34] - PA2 [pin 35] - PA3 [pin 36] - PA4 [pin 37] - PA5 [pin 38] - PA6 [pin 40] - PA7 [pin 41] - PB0 [pin 95] - PB1 [pin 96] - PB2 [pin 91] - PB3 [pin 92] - PB4 [pin 121] - PB5 [pin 120] - PC0/TCK/SWCLK [pin 100] - PC1/TMS/SWDIO [pin 99] - PC2/TDI [pin 98] - PC3/TDO/SWO [pin 97] - PC4 [pin 25] - PC5 [pin 24] - PC6 [pin 23] - PC7 [pin 22] - PD0 [pin 1] - PD1 [pin 2] - PD2 [pin 3] - PD3 [pin 4] - PD4 [pin 125] - PD5 [pin 126] - PD6 [pin 127] - PD7 [pin 128] - PE0 [pin 15] - PE1 [pin 14] - PE2 [pin 13] - PE3 [pin 12] - PE4 [pin 123] - PE5 [pin 124] - PF0 [pin 42] - PF1 [pin 43] - PF2 [pin 44] - PF3 [pin 45] - PF4 [pin 46] - PG0 [pin 49] - PG1 [pin 50] - PH0 [pin 29] - PH1 [pin 30] - PH2 [pin 31] - PH3 [pin 32] - PJ0 [pin 116] - PJ1 [pin 117] - PK0 [pin 18] - PK1 [pin 19] - PK2 [pin 20] - PK3 [pin 21] - PK4 [pin 63] - PK5 [pin 62] - PK6 [pin 61] - PK7 [pin 60] - PL0 [pin 81] - PL1 [pin 82] - PL2 [pin 83] - PL3 [pin 84] - PL4 [pin 85] - PL5 [pin 86] - PL6 [pin 94] - PL7 [pin 93] - PM0 [pin 78] - PM1 [pin 77] - PM2 [pin 76] - PM3 [pin 75] - PM4 [pin 74] - PM5 [pin 73] - PM6 [pin 72] - PM7 [pin 71] - PN0 [pin 107] - PN1 [pin 108] - PN2 [pin 109] - PN3 [pin 110] - PN4 [pin 111] - PN5 [pin 112] - PP0 [pin 118] - PP1 [pin 119] - PP2 [pin 103] - PP3 [pin 104] - PP4 [pin 105] - PP5 [pin 106] - PQ0 [pin 5] - PQ1 [pin 6] - PQ2 [pin 11] - PQ3 [pin 27] - PQ4 [pin 102] - RBIAS [pin 59] - VBAT [pin 68] - VDD_1 [pin 7] - VDD_10 [pin 79] - VDD_11 [pin 90] - VDD_12 [pin 101] - VDD_13 [pin 113] - VDD_14 [pin 122] - VDD_2 [pin 16] - VDD_3 [pin 26] - VDD_4 [pin 28] - VDD_5 [pin 39] - VDD_6 [pin 47] - VDD_7 [pin 51] - VDD_8 [pin 52] - VDD_9 [pin 69] - VDDA [pin 8] - VDDC_1 [pin 87] - VDDC_2 [pin 115] - VREFA+ [pin 9] - XOSC0 [pin 66] - XOSC1 [pin 67] ### U2 — [MP4560DN-LF-Z](https://www.flux.ai/monolithicpower/mp4560dn-lf-z~fyc.md) - Manufacturer Part Number: MP4560DN-LF-Z - Datasheet URL: https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/MP4560 - Package or Case Code: SOIC8E_MP4560_MNP - Product Info Url: https://www.monolithicpower.com/en/catalog/product/view/id/152?utm_source=ultralibrarian&utm_medium=component_search&utm_campaign=listing - Manufacturer Name: Monolithic Power Systems - Product Image Url: https://www.monolithicpower.com/pub/media/catalog/product/M/P/MP4560_152_1_2.jpg **Pins:** - BST [pin 8] - COMP [pin 3] - EN [pin 2] - EPAD [pin EPAD] - FB [pin 4] - FREQ [pin 6] - GND [pin 5] - SW [pin 1] - VIN [pin 7] *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/vishnu007/2-layer-jlcpcb-constraints-rzdr~4r](https://www.flux.ai/vishnu007/2-layer-jlcpcb-constraints-rzdr~4r).* --- *Generated from [https://www.flux.ai/vishnu007/2-layer-jlcpcb-constraints-rzdr~4r](https://www.flux.ai/vishnu007/2-layer-jlcpcb-constraints-rzdr~4r)*