NOT ROUTE-READY. This bounded batch is finished; the overall routing/design task is not finished. No full-board autoroute was started. Component placement, board outline, eight mounting reservations, schematic connectivity and manufacturing limits were preserved. No board configuration/copper changes persisted: the fresh neckdown generation call returned 0 generated neckdowns. Documentation is the applied change.

Read-only verification: full DRC/Placement/ERC/Signal Integrity query at 2026-10-09T03:12:30.934Z, final paged query at 03:18:00.794Z (176 Error/Warning items total), and final airwire/redundancy/stackup query at 03:18:40.495Z. Feasibility check performed twice, before and after neckdown execution: identical three USB warnings. Error means wrong; Warning means possibly wrong, but pin-removal warnings are a functional routing gate.

175 Error items + 1 Warning in queried DRC/Placement/ERC/Signal Integrity categories. The three feasibility warnings are separate, not included in that 176. No additional Error/Warning appeared in these categories. Final focused airwire/redundancy/stackup query has 153 total Error/Warning items, all airwires; no redundancy or stackup-validation finding. No routed critical nets. No GND airwires appear in routing_state. USB_DP and USB_DM each retain four airwires.

J1 ERC pins: GND, GND__1, SHELL_GND and its three additional shell pins on GND; VBUS and VBUS__1 on USB_VBUS. These and the IMU source-detection issues remain visible and unsuppressed; routing preparation does not resolve logical source declarations.

Live roles are Top Signal / Mid-Layer 1 Ground Plane / Mid-Layer 2 Ground Plane / Bottom Signal. Copper thicknesses are four ×0.035mm. Dielectrics are 0.210mm FR-4 Dk4.4 / 1.065mm Core Dk4.6 / 0.210mm FR-4 Dk4.4. Masks are two ×0.025mm Dk4. Through-via configuration remains 0.55mm pad, 0.25mm drill L1–L4; hole configuration 0.25mm.

New exact reconciliation: computed.substrateThickness = 1.555mm = 0.210 + 1.065 + 0.210 + 2×0.035. This is precisely the dielectric plus inner copper sum, excluding the two outer copper layers. Displayed totalThickness = 1.55mm is consistent with that aggregate at limited display precision. Full copper-plus-dielectric sum = 1.625mm; adding masks = 1.675mm, excluding silk/paste. The numerical discrepancy is therefore accounted for; the documentation/tool label semantics are not independently confirmed. Do not change core/dielectric values merely to force 1.55mm: that would be an unnecessary physical redesign. Do not claim that 1.55mm is finished thickness or that the actual fab guarantees these Dk/geometry values. Prior custom stackup reapply was not repeated.

Manufacturing selections remain Standard Density SDI v3 and JLCPCB SDI 4 Layer v1. Native configuration confirms copper layer IDs: Top, Mid-Layer 1, Mid-Layer 2, Bottom. Three help searches found no authoritative aggregate-thickness definition. Internal engineering-feedback submission failed again; no ticket/report was filed.

These preserve prior core-only current allocation and SDI minimum 0.127mm. No motor-current path or accessory-current allocation is implied. Fresh generator still authored zero deterministic neckdowns.

Current J6 summary still uses origin(-6.35,-17) as a centered 16.04×3.19mm proxy, producing proxy X=-14.37…1.67. The actual library uses pin1 datum with local pad X=0…12.7 and courtyard X approximately -1.67…14.37 (prior placement file's exact inspection). Actual centered row is X≈±8.02 after translation. The checker reports two reservation Errors on every J2–J7 despite that footprint-origin issue. No rule safely fixes checker datum without changing physical copper or suppressing checks. Required fix is an origin-aware bounds calculation upstream, or separately approved/qualified centered-datum part replacement, not moving the current headers based on incorrect proxies.

Live connector UID: 0168a5e7-c867-4b64-8a01-769dfddabd45.

Live schematic confirms reciprocal partner names and inherited target 90Ω, tolerance7.5%, pair data / USB2. Both inherit Pair Role D1; no guessed polarity rewrite made. Feasibility warnings remove J1 DP1/DN2, J1 DP2/DN1 and U1 PA12/PA11 from routed nets. These cannot be accepted as harmless.

Prior protected breakout diagnostic: “foreign copper blocks every tie/Y/wraparound candidate.” That result did not identify the copper or requested geometry. Fresh tree contains only GND fill and three fill-generated vias, zero existing signal traces and polygons, so there is no proven redundant trace cleanup capable of fixing it. Do not delete GND fill/vias or connector pads on speculation.

Fresh 2D data: J1 data pads are0.30mm wide, centers X=-0.75,-0.25,+0.25,+0.75 nearY12.145, pad lower edge≈11.565. D2 upper DP pad copper extends Y10.15…10.75 at X=-1.75…-0.55 and0.55…1.75; central corridor below J1 therefore offers≈0.815mm before D2 upper copper. U1 PA11/PA12 are centered at(5.67,2.75)/(5.67,3.25), 0.28mm pad width,0.50mm pitch. The GND via at(-4.5,10.5) is not a demonstrated central tie obstruction. These coordinates narrow the investigation; they do not prove which object blocks every candidate.

A specific diagnostic placement candidate, ONLY after approval and clearance review, is moving D2 from(0,9.5) to(-2.0,9.0)mm, retaining its side/rotation. This shifts D2 copper away from the connector's central southbound corridor and increases the raw J1-to-upper-D2-copper vertical interval by0.50mm. However, its courtyard may then conflict with U1, and it does not address U1's separate pin warning. It is not a qualified or recommended blind move, and was not applied. Obtain candidate breakout polygons/blocking-node diagnostics first; then approve a geometry-backed move. No claim of a precise cured obstruction is possible from the current tool output.

Do not launch main autoroute now. First resolve/prove USB escape and origin-aware keepout gate. After qualified preparation and a fresh acceptable feasibility check, current main API accepts exactly:

JSON
{"action":"start","startNewCampaign":false,"layerOrientations":[{"layer":"Top","orientation":0},{"layer":"Bottom","orientation":90}]}

run_auto_route has no layerPreferredNets, subset-net, keepout or allow-warning argument in its current schema. Do not invent such arguments. If a job already exists, resume it instead of start/cancel. Targeted mutate_layout_routes requires the same orientations and critical-net layer preferences. Preserve protected breakout copper once successfully authored. No routing campaign reset authorized.

Exact Ø4mm side-open notch/hole geometry,39mm mating envelope,30.5mm hardware fit, header/socket/cable access,bottom clearance,4.9mm reference-height compatibility, unequal-size ESC interface, firmware/app compatibility and all flight/55A performance remain unverified. This file is a blocked preparation handoff, not a fabrication or flight release.