188 official pins are correctly mapped by number and function; 56 names have suffix/case formatting differences.
The extra 22 EP terminals (189–210) are valid central ground-copper geometry but are incorrectly modeled as numbered electrical pins.
All terminals lack pin descriptions and use Pin Type = Unspecified.
Mount = Wire is incorrect; this is an SMD/castellated module. Part Type is unset.
The footprint’s 188 perimeter pads, 0.8 mm pitch, and primary land geometry match the datasheet.
The stored Datasheet URL points to the wrong SAMA5D2 SiP datasheet. It was not changed because the requested condition was to update it only if absent.
The 3D model could not be fully validated because its referenced asset was unavailable.
Datasheet URL update — unattempted by constraint. The field is not absent, so the instruction “Only update the Datasheet URL if missing” prohibits changing it. The stored URL was nevertheless verified and is the wrong document (details below).
Exhaustive terminal number/name comparison — completed for all 210 project terminals.
Pin Description / Pin Type comparison — completed for all 210 terminals.
Footprint comparison — completed for all inspectable 2D geometry.
3D model comparison — partially blocked: the footprint references ATSAMA5D27-WLSOM1.stp, but no STEP/GLB model asset is present in the project asset list, so model dimensions and rendered orientation could not be inspected.
The PDF extraction returned page/table evidence but no immutable Flux citation IDs. Accordingly, evidence below is identified by the official document’s table/figure numbers rather than unsupported inline citation markers.
Part-level metadata
Table
Property
Current project value
Audit result
Project/name
ATSAMA5D27-WLSOM1
Correct
Manufacturer Part Number
ATSAMA5D27-WLSOM1
Correct
Manufacturer Name
Microchip
Correct; official branding is Microchip Technology Inc.
Package or Case Code
Module
Consistent with the SOM
Description
SAMA5D2 Wireless SOM - Embedded Module ARM Cortex-A5 500MHz 256MB 8MB
Broadly consistent: 2 Gbit LPDDR2 = 256 MB and 64 Mbit SQI flash = 8 MB. It omits Wi-Fi/BT, Ethernet PHY, secure element, dimensions, and voltage/temperature details.
Pin/terminal count
210
Does not match the official numbered pad count of 188; explanation below
Datasheet URL
Google Storage PDF (...27c748...pdf)
Confirmed wrong document. Querying the stored URL returns the SAMA5D2 SiP Data Sheet DS60001484E (11/2025), not the ATSAMA5D27-WLSOM1 module datasheet DS60001590D. Not changed because the field is present and the scope permits an update only when absent.
Mount
Wire
Confirmed metadata mismatch. This is a surface-mount castellated/SMD module, not wire-mounted.
Designator Prefix
IC
Acceptable, though U is a more common convention
Symbol Style
parametric-v1
Present
Part Type
absent
Confirmed by Component Review Check warning: “Part Type is not set”
Official key specifications
SAMA5D27 Arm Cortex-A5 based MPU/SIP, up to 500 MHz.
2 Gbit LPDDR2-SDRAM (256 MB).
64 Mbit Serial Quad I/O flash (8 MB).
ATWILC3000 Wi-Fi 802.11 b/g/n and Bluetooth 5 subsystem.
Main operating input 3.0–5.5 V ±5%; operating temperature −40°C to +85°C.
Module body 40.8 × 40.8 mm nominal; 3.287 mm nominal total thickness; 0.8 mm perimeter-pad pitch.
Exhaustive terminal comparison
Numbering and presence
Official Table 4-1 defines exactly 188 numbered pins, 1–188.
Project terminals 1–188 are all present exactly once; no missing or duplicate pin numbers were found.
After normalizing CAD uniqueness suffixes, all 188 project terminal names map to the correct official signal for their pin number.
Project terminals 189–210 are additional EP terminals and are not in official Table 4-1.
Exact name mismatches within pins 1–188
The following are exact-string differences from Table 4-1:
All 46 GND pins use unique project names GND_1 through GND_46 instead of the official repeated name GND.
Pins 2, 3, 4 use VDD_MAIN_1, VDD_MAIN_2, VDD_MAIN_3 instead of VDD_MAIN.
Pins 12, 13 use _VDD_3V3_1, _VDD_3V3_2 instead of VDD_3V3 (extra leading underscore and uniqueness suffix).
Pins 185, 186 use VDD_DDR_1, VDD_DDR_2 instead of VDD_DDR.
Pin 97 is SIO3_QSPI_PB10_ instead of SIO3_QSPI_PB10 (extra trailing underscore).
Pin 100 is SIO2_QSPI_PB9_ instead of SIO2_QSPI_PB9 (extra trailing underscore).
Pin 182 is NSTART_SOM instead of the datasheet spelling nSTART_SOM (case mismatch).
Thus, 132 of 188 names are exact string matches and 56 differ only by the listed suffix/prefix/case formatting. No pin 1–188 was mapped to a different functional signal.
Pin descriptions and electrical types
Pin Description is absent on all 210 terminals. The official Table 4-1 provides a description for every numbered pin 1–188.
Pin Type is Unspecified on all 210 terminals. The official table classifies pins as GND, input, output, I/O, system, NC, Ethernet, or USB.
Therefore, the project has 188 missing descriptions and 188 non-specific electrical types for the official pins. EP terminals 189–210 also have no descriptions and are Unspecified.
Footprint audit
Correct perimeter geometry (pads 1–188)
The imported footprint’s perimeter lands agree with official Figure 6-2 / Table 6-3:
Count and numbering: pads 1–188, continuous and unique.
Pitch: 0.8 mm.
Copper land size: 0.600 × 2.000 mm.
Land centers: ±19.900 mm from the footprint origin on each side.
This yields 37.800 mm between inward pad ends, matching S1/S2.
Adjacent 0.600 mm lands on 0.800 mm pitch leave 0.200 mm copper spacing, matching k.
Numbering proceeds around all four sides consistently with the footprint source and pin-1 corner marking.
Confirmed footprint mismatches / omissions
Pads 189–210 are incorrectly represented as numbered electrical terminals. The official numbered module pad count is 188. The central shapes correspond to GND-pad layout geometry shown in Figures 6-2/6-3, but they are not pins 189–210 in Table 4-1.
The six 1.6 × 1.6 mm central lands (project pads 189–194) and sixteen 0.8 × 0.8 mm lands (195–210) have coordinates that match the coordinate callouts visible in the official land-pattern drawing. Their physical geometry appears intentional and datasheet-derived, but their numbering and EP terminal mapping are erroneous. They should be treated as GND copper features rather than new module signal pins.
The footprint asset contains no inspectable full 40.8 × 40.8 mm body/fabrication outline; only a minimal pin-1 silkscreen mark is present. Therefore, body outline compliance cannot be visually verified from 2D outline primitives.
The footprint does not encode the official inner keepout as an inspectable keepout rule. The datasheet states that no signal/power vias or tracks are allowed in the S1/S2 interior except for the recommended GND treatment.
No explicit solder-mask opening rule for the 0.550 mm solder-mask-defined opening was visible in the imported KiCad footprint text; pads use F.Mask without a local mask margin. Whether the platform/global mask settings produce the required opening is uncertain.
Pads 189–210 determination
Conclusion: These 22 central shapes are not valid numbered pins 189–210 and are not the ten production test points. Their positions and sizes correspond to the official GND-pad layout geometry, while the datasheet separately specifies only 188 numbered perimeter pads and 10 production test points that must not be connected. The project’s central copper geometry is plausibly valid, but exposing it as 22 independent EP_* terminals increases the part’s terminal count incorrectly and misrepresents the electrical interface.
3D model
Footprint text references ATSAMA5D27-WLSOM1.stp at zero X/Y rotation and scale 1.
The referenced model is not present in the current project asset list, and no Model node dimensions were inspectable.
Uncertain/uninspectable: actual model body size, height, seating Z, pin-1 orientation, U.FL orientation, and footprint-to-model alignment.
Confirmed errors vs uncertain items
Confirmed errors
Stored Datasheet URL resolves to the wrong Microchip document (SAMA5D2 SiP DS60001484E, not WLSOM1 DS60001590D).
Project has 210 terminals instead of the official 188 numbered pins.
EP terminals/pin numbers 189–210 are not defined in the official pin table.
Mount = Wire is inconsistent with the SMD module land pattern.
Project-level Part Type is absent.
Uncertain or uninspectable
3D model dimensions, seating, and orientation because the referenced model asset is unavailable.
Effective solder-mask opening for the 0.550 mm SMD requirement because no local mask margin was inspectable.
Full body-outline alignment because no complete body/fabrication outline primitive was present.
Change log
No project properties or geometry were changed. The Datasheet URL field was present, so changing it would violate the explicit “Only update the Datasheet URL if missing” scope restriction. The correct replacement value, if correction is later authorized, is: