I’ll treat each lock as a 4-wire 24 V device: two coil wires plus two 24 V lock-state wires. I’ll add 16 protected 24 V-tolerant state inputs using input shift registers, update the connectors/interface docs, and verify the schematic changes.
I’m adding isolated 12/24 V state sensing: each state wire drives an optocoupler input, and two 74HC165 input shift registers report the 16 states to the ESP32-S3.
Updated the design for 4-wire 12/24 V locks: each lock now has coil drive plus isolated 12/24 V state sensing, read through two 74HC165 input shift registers. I also updated the project specification, firmware starter, bring-up plan, and FMEA; validation now shows only expected unused ESP32 dev-board pin warnings.
Estimated time saved vs. manual EDA workflow: ~4–6 hours.
Open items:
Confirm state polarity: whether the 24 V state signal means “locked” or “unlocked.”
Confirm real lock coil current and max simultaneous activations.
Finalize the buck regulator values before PCB layout.
Suggested next steps:
Define the exact connector pinout labeling/silkscreen.
Finalize U2 regulator passives from the datasheet.
Place the 16 lock connectors and high-current driver section on the PCB.
Add firmware CAN command handling and state reporting.