Project Specification — Multi-Lock Controller
Purpose
Functionally similar electronic lock controller inspired by the photographed locker check board, implemented as a clean new design rather than a clone.
Current Architecture
- 12/24 V DC lock supply input through terminal block, fuse, TVS, and bulk capacitance.
- 3.3 V logic rail generated from the lock supply using LMR33630 buck-regulator block.
- ESP32-S3 DevKitC main controller for USB programming, control firmware, test mode, CAN/TWAI, lock drive, and lock-state scanning.
- Two SN74HC595 shift registers provide 16 lock-control outputs.
- Sixteen low-side N-MOSFET channels switch 12/24 V locks/solenoids.
- Each output channel includes a gate resistor, gate pulldown, flyback diode, and dedicated 4-wire lock connector.
- Each lock connector is now intended as: pin 1 = +12/24 V coil supply, pin 2 = switched coil return, pin 3 = 12/24 V state+, pin 4 = state-.
- Sixteen optocouplers isolate the 12/24 V lock-state signals from 3.3 V logic.
- Two 74HC165 parallel-in/serial-out shift registers report the 16 isolated lock-state bits to the ESP32-S3.
- CAN transceiver and 2-pin CAN connector are included.
- 8-position DIP switch provides active-low configuration inputs.
Assumptions
- Locks may be 12 V or 24 V, but the controller power input and state input conditioning are designed around 24 V-tolerant operation.
- Output count: 16 lock/solenoid channels.
- Lock outputs are low-side switched; external locks connect between +12/24 V and the switched return.
- Lock state output is treated as a 12/24 V signal that drives an optocoupler input.
- Simultaneous lock activation must be limited in firmware unless the power supply, fuse, connectors, and copper are upsized.
Important Open Engineering Items
- Regulator passives are still preliminary; the LMR33630 feedback network, BOOT capacitor, VCC capacitor, compensation/PG handling, and inductor/current ratings need datasheet-final verification before PCB layout.
- Actual lock current is unknown; MOSFET thermal design, fuse rating, connector current rating, and trace width must be adjusted once lock current and simultaneity are defined.
- Confirm whether the lock-state wires are polarity-sensitive and whether state asserted means locked or unlocked.
- CAN termination should be made selectable if this board may be used in the middle of a CAN bus.
- Final PCB layout needs high-current copper pours and separated logic/power-current routing.