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flux

This session established the actual release state and completed the crystal correction, but the board is not yet fab-ready.
  • Independent audit confirmed the original USB route has four asymmetric through-vias, approximately 3.4 mm skew, variable geometry, and loose coupling. A fabrication impedance note cannot make that production-safe.
  • The 32.768 kHz crystal block was rebuilt successfully: X1/C15/C16 placement and XL1/XL2 are now short, local, Top-only, and via-free.
  • The USB rebuild exposed a D+/D− pin-order crossover between J1, U7, and U1. Reorienting U7 and restoring the displaced routes was launched, but I could not retrieve and independently reconcile its final report.
  • The last confirmed intermediate state was commit #7214da2f with 13 airwires, so manufacturing exports were correctly withheld.
  • BOM consolidation/mapping issues also still require correction before PCBA release.
Remaining release work:
  1. Confirm the latest live routing state and restore any remaining airwires.
  2. Complete USB as a Top-only, via-free, consistently coupled pair with ≤0.5 mm skew.
  3. Correct BOM grouping and remaining LCSC mappings.
  4. Run fresh independent ERC, DRC, route-layer, RF, footprint, and assembly audits.
  5. Generate and inspect Gerber/drill, BOM, and pick-and-place files.
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Files

Schematic

Layout

3D View

Architecture Proposal

Table

BlockRecommended partJLCPCB / placement note
MCU + BLEEbyte E73-2G4M08S1C (nRF52840 module)LCSC C356849, JLCPCB Extended. Preferred over Raytac for assembly sourcing. Native USB D−/D+ are exposed on module pins 29/31.
GNSSu-blox DAN-F10N-00BNot shown with distributor stock in the Flux library; assume customer-supplied / hand-placed unless JLCPCB confirms procurement. Main VCC is 2.7–3.6 V and startup inrush may reach 100 mA.
IMUST LSM6DSO32TRLCSC C1864162, JLCPCB Extended. Proposed substitute because the exact LSM6DS3TR-C was not found as a verified Flux/JLC part. 2.5 × 3.0 mm LGA, I2C at 3.3 V.
PDM microphoneKnowles SPH0641LM4H-1LCSC C497724, JLCPCB Extended. Bottom-port orientation and acoustic PCB opening must be checked during layout.
Fuel gaugeMAX17048G+T10LCSC C2682616, JLCPCB Extended, 2 × 2 mm TDFN. Connect directly across the battery so state-of-charge remains available independently of the load switch.
ChargerMCP73831T-2ATI/OTSOT-23-5, LCSC-supported. Charge current set by RPROG after battery capacity is known.
3.3 V LDOAP2112K-3.3TRG1SOT-23-5, LCSC-supported, 600 mA rating.
USB ESDUSBLC6-2P6SOT-666, LCSC-supported.
USB-CTYPE-C-16M-0243MDLCSC C2798172, JLCPCB Extended; USB 2.0 + power-only pin set.
Battery connectorJST S2B-PH-SM4-TB(LF)(SN)LCSC C295747, JLCPCB Extended.
Power switchC&K JS102011JCQNCompact SMD slide switch; verify current JLC stock.
User input / indicatorTS-1088-AR02016 tactile switch + NCD0402R1 red LEDBoth LCSC/JLCPCB Extended.
Block-level schematic
Diagram



  
    
  
  
    
  



















VBUS

D+ / D- through USBLC6-2

UART crossed

Shared I2C

Shared I2C

PDM CLK + DATA













USB-C receptacle
MCP73831 charger
1-cell LiPo / JST
MAX17048 fuel gauge
Slide power switch
AP2112K 3.3 V LDO
3V3 rail
E73 nRF52840 BLE module
DAN-F10N GNSS
LSM6DSO32 IMU
PDM microphone
SWDIO / SWDCLK / RESET / node_3V3 / GND
LED + push-button
Planned electrical details
  • USB-C: CC1 and CC2 each use 5.1 kΩ to GND. D+/D− pass through USBLC6-2P6 to the E73 USB pins. USB VBUS also feeds the E73 VBUS sense/input pin while the module itself is powered from switched 3V3.
  • Power: USB VBUS feeds MCP73831 VIN. Charger BAT connects to the LiPo node. The MAX17048 remains on the unswitched battery node. The slide switch disconnects the system load before the AP2112K. Use local input/output bulk and 0.1 µF high-frequency bypassing.
  • GNSS: DAN-F10N VCC pins 52/53 connect to 3V3; V_BCKP connects to 3V3 for the first build; RXD pin 9 connects to nRF TX and TXD pin 10 to nRF RX. All module GND pins connect to the solid ground system. Use the requested 10 µF + 0.1 µF at VCC.
  • I2C: One shared 4.7 kΩ pull-up pair from SDA/SCL to 3V3 for the IMU and MAX17048. The proposed IMU requires CS tied high for I2C, with SCL/SDA externally pulled to VDDIO.
  • IMU: VDD and VDDIO at 3V3, each with 100 nF local decoupling; SA0 tied low for address 0x6A.
  • Microphone: 3V3 with 0.1 µF local bypass; PDM clock and data assigned to free nRF52840 GPIOs; channel-select strapped for a single channel.
  • Debug and test: compact 1.27 mm SWD footprint or Tag-Connect pads; test points for 3V3, GND, and GNSS UART TX.
  • User interface: red 0402 LED driven from U1 P1.13 on MCU_STATUS_LED_DRIVE through approximately 1 kΩ; momentary switch shorts its assigned GPIO to GND and firmware enables the internal pull-up. Firmware must configure nRF52840 P1.13 as the status-LED output; the former P0.13 assignment is retired.
Layout implications
  • Put the DAN-F10N at a board edge with an uninterrupted ground plane beneath it. Its optimum antenna reference is a 70 × 70 mm ground plane, and smaller boards reduce antenna gain/efficiency. This is the main conflict with “smallest possible footprint”; the board can be much smaller, but GNSS performance must be validated on the actual wearable enclosure and body position.
  • Put the E73 antenna end at the opposite board edge. Keep copper, battery, switch, USB cable region, and fast/power routing away from the antenna end; the E73 guidance explicitly warns against power and high-frequency routing beneath the module and nearby EMI sources.
  • Keep the microphone acoustic port clear with its required PCB opening and enclosure vent.
  • Use four layers: top signal/components, inner-1 solid GND, inner-2 power/slow signals, bottom signal; preserve continuous GND beneath GNSS.
Decisions needed before schematic capture
  1. IMU: approve LSM6DSO32TR as the JLC-friendly substitute, or require the exact LSM6DS3TR-C as a customer-supplied/hand-placed part.
  2. Battery capacity: needed to set MCP73831 charge current safely. Proposed default for a small wearable is 100 mA charge current until the cell is selected.
  3. Debug connector: proposed default is a Tag-Connect-style 6-pad footprint rather than a populated pin header to minimize board area.
Known constraints and risks
  • The DAN-F10N dominates board area and antenna performance; “smallest possible” and best dual-band GNSS sensitivity are competing goals.
  • MCP73831 has no power-path management. The tracker may operate while charging, but charger termination behavior can be affected by system load. This follows the requested topology; a dedicated power-path charger would be a more robust but larger architectural change.
  • Live JLCPCB stock and Basic/Extended classification must be rechecked immediately before ordering.

  • Recommended part selection

  • Block-level schematic

  • Planned electrical details

  • Layout implications

  • Decisions needed before schematic capture

  • Known constraints and risks