# EEG Digital ## Description Two-PCB low-noise EEG system: Digital board (ESP32-S3-MINI-1U + ADS1299 + CP2102N + USB-C + 1S Li-ion charger/power-path + DF40 mezzanine) and Analog board (3x ADS1299 + REF/BIAS/DRL + driven-shield electrode interfaces + local low-noise regulation + test points). DF40 mezzanine carries only power + digital SPI/control with shared SPI, shared START/RESET, and separate CS/DRDY per AFE. 4-layer stacks with strong analog/digital partitioning and interleaved GND pins on DF40. ## Project Details - **Owner:** theemeraldhunter - **Created:** 2/16/2026 - **Last Updated:** 2/16/2026 - **Visibility:** Public - **Mezzanine Connector:** Hirose DF40 ~60-pin, 0.4 mm pitch, interleaved GND - **SPI Topology:** Shared SCLK/MOSI/MISO; separate CS and DRDY per ADS1299; common START and RESET. - **System Architecture:** ```mermaid flowchart TD subgraph DigitalBoard [Digital Board] USB_C["USB-C Connector"] TVS_USB["Low Cap TVS D+ D-"] CHG_PP["1S Charger PowerPath Prot"] BAT["1S Li-ion Battery"] REG_3V3D["3V3 Digital Regulator"] REG_3V3A["3V3 Analog Regulator"] ESP32["ESP32-S3-MINI-1U"] ADS_D["ADS1299 x1 Digital Board"] CP2102N["CP2102N USB-UART"] MEZZ["DF40 Mezzanine 60-pin"] ESD_ELEC_D["Electrode Pads and ESD"] end subgraph AnalogBoard [Analog Board] MEZZ_M["DF40 Mate"] REG_LN["Low Noise Regulators"] FILT["Ferrite and RC Filters"] ADS_A1["ADS1299 A1"] ADS_A2["ADS1299 A2"] ADS_A3["ADS1299 A3"] ELEC_NET["Electrode Input Networks"] DRL_BIAS["REF BIAS DRL Driven Shield"] TP["Test Points"] end USB_C --> TVS_USB USB_C --> CHG_PP CHG_PP --> BAT CHG_PP --> REG_3V3D CHG_PP --> REG_3V3A USB_C --> CP2102N REG_3V3D --> ESP32 REG_3V3A --> ADS_D ESP32 --> ADS_D ESP32 --> MEZZ ADS_D --> MEZZ REG_3V3A --> MEZZ REG_3V3D --> MEZZ MEZZ --> MEZZ_M MEZZ_M --> REG_LN REG_LN --> FILT FILT --> ADS_A1 FILT --> ADS_A2 FILT --> ADS_A3 MEZZ_M --> ADS_A1 MEZZ_M --> ADS_A2 MEZZ_M --> ADS_A3 ADS_A1 --> ELEC_NET ADS_A2 --> ELEC_NET ADS_A3 --> ELEC_NET ELEC_NET --> DRL_BIAS DRL_BIAS --> TP ``` - **Layer Count:** 4-layer - **USB-C Policy:** USB2.0 data with CC resistors and low-cap bidirectional TVS on D+/D-; includes ESD on VBUS as needed. - **Stackup Intent:** Digital+Analog partitioned planes (GND + split power) - **Notes:** EEG front-end uses ADS1299; analog board includes REF/BIAS/DRL and driven-shield electrode networks; include test points. - **Battery Power:** 1S Li-ion with charger + power-path + protection - **Interconnect Policy:** Mezzanine carries only power and digital signals (SPI/control). No analog electrode signals across DF40. *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/theemeraldhunter/eeg-digital](https://www.flux.ai/theemeraldhunter/eeg-digital).* --- *Generated from [https://www.flux.ai/theemeraldhunter/eeg-digital](https://www.flux.ai/theemeraldhunter/eeg-digital)*