Circuit Diagram Extraction

Thought for 41 sec

I think there’s a typo in your message: you wrote “Emitter 2 to VIN and Emitter 2 to VIN”.

From the live schematic, the current wiring is:

Table

BCV62 pin	Meaning in wrapper	Current schematic net
`Q1:C2`	`P1 = B1 = B2 = C2`	`Net 1`, through R1 to GND
`Q1:C1`	`P2 = C1`	`Net 2`, Q2 gate + R2
`Q1:E1`	`P3 = E1`	`Net 3`, Q2 drain
`Q1:E2`	`P4 = E2`	`Net 4`, Q2 source

So right now:

Text
E1 = Net 3 = Q2 drain
E2 = Net 4 = Q2 source

In our previous simulation setup, we treated:

Text
Net 3 = VIN
Net 4 = VOUT

So the current schematic is:

Text
E1 = VIN
E2 = VOUT

If your intended wiring is E2 to VIN, then the simulation mapping should instead treat:

Text
Net 4 = VIN
Net 3 = VOUT

or the schematic needs E1/E2 swapped.

That distinction is exactly why the previous VIN = 0V, VOUT = 5V operating point turned the PMOS on: under the mapping I used, the gate-drive transistor had E1 tied to VIN instead of the higher VOUT node.

Can you confirm which one you meant?

E1 to VIN, E2 to VOUT — current schematic as previously simulated
E2 to VIN, E1 to VOUT — likely the intended reverse-blocking behavior
Something else — tell me which BCV62 emitter pin goes to VIN and which goes to VOUT

Use E2 as VIN

Verify Q1 pinout

Simulate reverse blocking

Inspect Q1 nets

Files

Schematic

Layout

3D View

Resistance

47KΩ

Resistance

10KΩ

VOUT

VIN

spice-testing