I’m sorry, but I don’t have direct access to interpret that PDF attachment. However, I can offer some general tips on why a J-Link might not connect to an nRF-based board:
SWD Pins Not Connected Properly
Verify that the SWDIO and SWCLK lines go directly to the chip’s corresponding pins and are not accidentally swapped or left floating.
Ensure that you have connected ground reference (GND) and the same supply reference (3.3 V or similar) between the J-Link and your board.
No or Incorrect Pull Resistors
While not always essential for every design, some reference designs call for small pull-ups or pull-downs on SWD lines or the RESET pin to ensure stable levels.
If you see random lines floating on the schematic or hardware, adding a small pull-up (e.g., 10 kΩ) to the supply rail or a pull-down to ground may help.
Missing or Incorrect Power Supply / Decoupling
Double-check the power supply arrangement to the nRF chip. If it’s under-voltage, the chip may not respond to SWD.
Look at the decoupling capacitors on VDD pins; insufficient decoupling sometimes causes reliability issues.
Reset / Debug Pin Configuration
If a manual reset or certain boot configuration is required, confirm the reset line or any special pins. If the chip remains in a reset state, J-Link can’t connect.
In some designs, the SWD pins might be repurposed if specific fuse settings or code accidentally reconfigure them. That would also break SWD programming.
Incorrect Pin Layout
Mistakes can happen if your schematic labels SWDIO and SWCLK but accidentally routes them to the wrong pins on the nRF chip. Cross-check the pin numbering in the schematic vs. the actual chip datasheet.
J-Link Settings or Cable Issues
If you’re positive the schematic is correct, check the debug probe’s wiring. Even reversed or offset connections on a 2×5 header can prevent the J-Link from seeing the chip.
Ensure that the J-Link software is set for the right target voltage and interface speed.
Oscillator or Clock Issues
If you rely on an external crystal and it’s not starting up, sometimes the chip can look “dead” from the SWD perspective. Typically, an nRF52832 can still use the internal RC for SWD, but if something in the schematic is pulling the clock pins abnormally, that can hinder debug.
If you suspect a schematic net mix-up:
Check the SWD lines:
SWDCLK → nRF52 SWCLK pin
SWDIO → nRF52 SWDIO pin
RESET (if used) → nRF52 RESET pin
Common ground.
Verify supply rail and any net labeled as “VDD” or “3.3 V” truly goes to the nRF52 power pins, and that you have the correct decoupling capacitors.
By systematically verifying each of these points on your schematic, you’ll often catch the typical debug-connection mistakes—especially swapped lines, missing ground reference, or incorrect pin usage. If all standard checks look correct, it may come down to cable polarity or a more subtle layout issue (for example, a long trace or noise on SWDCLK without sufficient ground reference).