IoT Sensor Node Design


I understand what you want: not PCB layout, but a cleaner schematic drawing where parts are visually grouped and visibly connected instead of looking like floating islands.
Right now I can help with the electrical schematic/netlist, but I cannot reliably auto-arrange the schematic canvas into a polished human-readable drawing from here. The project is electrically connected through named nets, but Flux may still show components visually separated if the schematic view has not been manually organized.
What I can do next is one of these:
  1. Read-only schematic readability audit
    I’ll report which parts only look floating versus which are actually unconnected.
  2. Create a clean schematic organization plan
    I’ll give you exact functional blocks and where each component should go:
    • Power input/regulator
    • ATmega4808 core
    • RS-485 interface
    • I2C sensors/OLED
    • Solenoid driver
    • Fan driver
    • Connectors/programming
  3. Fix real schematic connectivity issues
    If any capacitors or parts are genuinely not connected to nets, I can reconnect them electrically.
For the visual schematic cleanup, the target organization should be:
  • Left: J1/J2 RS-485 + 12 V bus input/output
  • Upper-left: AMS1117 regulator, C5, C11, 3V3 rail caps
  • Center: U1 ATmega4808 with reset, UPDI, decoupling
  • Upper-right: I2C devices: U4, IC1, OLED1, R1/R2
  • Right: RGB LED and resistors
  • Lower-right: solenoid driver Q1/D1/J4 and fan driver Q2/D2/J6
  • Bottom: programming and external sensor connectors J3/J5
Important: the “floating capacitors” you see may already be electrically connected to 3V3/GND by net names. They only look floating because visible schematic wires were not drawn between them.
If you want, I can now run the read-only schematic readability audit and list every component that visually appears isolated but is electrically connected, plus any that are truly unconnected.
Run readability audit
Create organization plan
Check floating capacitors
Explain named nets
Run ERC review

U4
Not Recommended for New Designs
R13
Resistance
33Ω
LED1
R2
Resistance
4.7kΩ
D1
J2
R12
Resistance
33Ω
Q2
R4
Resistance
100 Ω
J1
R7
Resistance
10kΩ
R8
Resistance
10kΩ
R5
Resistance
100kΩ
R14
Resistance
100 ohms
R15
Resistance
10 kohms
R3
Resistance
120 Ω
R10
Resistance
1kΩ
R1
Resistance
4.7kΩ
R9
Resistance
10kΩ
R11
Resistance
10kΩ
Q1
R6
Resistance
33Ω
D2
Design Notes
Requirements
  • Board size: 45 mm x 35 mm
  • Stackup: 4-layer
  • Application: agricultural seedling tray monitoring node
  • MCU: ATmega4808 in TQFP-32
  • Input power: 12 V DC bus
  • Logic rail: 3.3 V
  • Communications: RS-485 Modbus RTU half-duplex
  • Local peripherals: local-only I2C sensors, 0.96 inch I2C OLED, status LED
  • Actuation: 12 V solenoid valve switched by MOSFET from MCU command
  • Manufacturing: JLCPCB SMT assembly compatible, LCSC sourced parts
  • Export target: KiCad
Partitioning
  • Top side: sensors, OLED display, status LED
  • Bottom side: MCU, power circuitry, RS-485 transceiver, valve driver
Power architecture
  • Use AMS1117-3.3 linear regulator, not a switching regulator
  • No inductor required
  • No regulator enable circuitry unless a separate requirement appears
  • Avoid switching power components in the 3.3 V rail implementation
Notes
  • I2C sensor bus remains local to the PCB and does not leave external connectors.
  • Keep top-side real estate prioritized for sensing openings and upward-facing display visibility through acrylic lid.
Selected parts
  • MCU: ATmega4808-AFR, TQFP-32
  • Regulator: AMS1117-3.3RG, SOT-223, LCSC C2977152
  • RS-485: MAX485CSA+, SOIC-8, LCSC C143494
  • Ambient light sensor: BH1750FVI-TR, WSOF6I
  • Temperature and humidity sensor: HDC1080DMBR, WSON DMB 6-pin 3x3 mm
  • Solenoid switch MOSFET: AO3400
  • Flyback diode: SS14LW RVG
  • Bus connectors: SM04B-SRSS-TB(LF)(SN), 4-pin JST SH, LCSC C160404
  • Soil connector: S3B-PH-SM4-TB(LF)(SN), 3-pin JST PH SMT
  • Solenoid connector: KF301-2P, 2-pin screw terminal
  • Programming header: Molex 22-28-4033, 3-pin 2.54 mm THT
Validation status
  • Layout size set to 45 mm x 35 mm
  • Stackup set to Standard 4 Layer
  • Power rule preserved: Use AMS1117-3.3 linear regulator, not a switching regulator. No inductor required.
  • Device map frozen: U3 = MAX485CSA+ only in SOIC-8; generic MAX485-class and alternate RS-485 transceivers are excluded
  • Core nets created for VIN_12V, 3V3, GND, I2C, RS-485, and solenoid drive
  • Sensor correction applied: U4 replaced by BH1750FVI-TR with ADDR tied low and DVI RC network (R10 = 1 kΩ to 3V3, C12 = 1 uF to GND)
  • Sensor correction applied: IC1 replaced by HDC1080DMBR with SDA/SCL on local I2C bus, NC pins floating, and exposed pad floating
  • U5 removed from schematic; legacy capacitance front end no longer used
  • ADC placeholders created on MCU: PF2 = soil moisture ADC, PF3 = condensation ADC
  • Remaining work includes identifying the exact external soil-moisture connector/copper-trace designators for final ADC source attachment, and assigning physical placement for top-side vs bottom-side partitioning before any layout action
  • Connector replacement applied: CN1, CN2, and CN3 removed from schematic
  • Final connector map applied: J1 and J2 = SM04B-SRSS-TB(LF)(SN) on VIN_12V/GND/RS485_A/RS485_B, J3 = soil moisture connector on 3V3/GND/SOIL_MOISTURE_ADC, J4 = KF301-2P on VALVE_LOW/VIN_12V, J5 = UPDI header on GND/UPDI/3V3
Implementation plan update
  1. Review existing design documents and schematic to ensure consistency with component selections.
  2. Update power regulation and MCU support circuits where needed.
  3. Enhance design verification steps with the following sub-steps:
    1. Connector Pinout Sanity Check: Verify and document the exact pin mapping for connectors J1, J2, J3, J4, and J5.
    2. Regulator Support Parts Check: Confirm that the AMS1117-3.3 regulator circuit includes a 100 uF capacitor on the VIN_12V input and a 22 uF capacitor on the 3V3 output.
    3. MCU Decoupling Check: Ensure that the ATmega4808 MCU has proper decoupling with 100 nF capacitors on both the VDD and AVDD pins.
    4. RS-485 Bias and Termination Check: Validate that R7 pulls RS485_A to 3V3, R8 pulls RS485_B to GND, and that a 120 ohm resistor (R3) is present across RS485_A and RS485_B with DNP option.
    5. PCB-side Layout Risks Flagging: Identify and flag PCB design risks including isolation concerns for the HDC1080 DAP, absence of copper zone for the BH1750, condensation trace exposure issues, and requirements for differential routing attention for RS485_A and RS485_B.
  4. Update schematic annotations and notes to document the review process and adjustments.
  5. Validate changes and update success criteria to reflect each of these five explicit checks.
Success criteria update
  • Connector pinout sanity: Exact pin mappings for J1/J2/J3/J4/J5 are verified and documented.
  • Regulator support: AMS1117-3.3 circuit includes 100 uF on VIN_12V and 22 uF on 3V3 output.
  • MCU decoupling: 100 nF capacitors are confirmed on both U1 VDD and AVDD pins of the MCU.
  • RS-485 bias and termination: R7 is pulling RS485_A to 3V3, R8 is pulling RS485_B to GND, and 120 ohm resistor R3 is applied across RS485_A and RS485_B with DNP option.
  • PCB-side risks: Identified flags for HDC1080 DAP isolation, lack of copper zone for BH1750, condensation trace exposure, and confirmed differential routing for RS485_A and RS485_B have been addressed.
Explicit layout instructions before routing
  • IC1 / HDC1080: DAP pad must connect to an isolated floating copper island and must never connect to the GND plane. Add a 1 mm PCB slot around the sensor area for airflow.
  • U4 / BH1750: place on the top layer facing upward. Keep solder mask clear over the photodetector window area.
  • Condensation sensor: implement two parallel exposed copper lines in a comb pattern on the top layer, 0.2 mm line width and 0.2 mm gap, with no solder mask. Connect one trace set to CONDENSATION_ADC and the other to GND.
  • RS485_A / RS485_B: route as a matched-length differential pair, keep the pair together, and keep it away from I2C traces.
  • Placement partition: place U4, IC1, LED1, and OLED1 on the top layer. Place U1, U2, U3, Q1, D1, all passives, J3, J4, and J5 on the bottom layer. Place J1 on the left short edge and J2 on the right short edge.
  • Requirements

  • Partitioning

  • Power architecture

  • Notes

  • Selected parts

  • Validation status

  • Implementation plan update

  • Success criteria update

  • Explicit layout instructions before routing