Replacing Vector Robot Brain Board
Worked for 1 min 54 sec
Created a project doc
Passive Wiretap Board Status
This board has been redesigned as a safe listen-only wiretap for the Vector head/body 4-wire cable. It no longer includes the ESP32-C3 or ac...
Done — I redesigned it as a passive listen-only wiretap.
What changed:
- Removed ESP32-C3 and level-shifter from the signal path.
- Kept only headers + protection resistors.
- Mapped the confirmed Vector wires:
- black
GND - red
VMAIN - white
BODY_RX - green
TX1.8
- black
- Routed the simplified PCB.
- Ran ERC/DRC checks: no errors/warnings came back in the checked categories.
Saved status here:
Passive Wiretap Board Status
Passive Wiretap Board Status
Open item:
- This is still a hand-wired/probe board, not the final drop-in Vector connector board.
Document, BOM, export
Create wiring guide
Check BOM cost
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Review manufacturability
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Interposer Layout Status and Blockers
Current Build Status
This project now contains a safe first-stage Vector reverse-engineering/debug interposer rather than a final smarter brain board.
Schematic
The schematic contains:
- ESP32-C3-WROOM-02-N4 helper/debug MCU
- TXB0104D 2.8 V ↔ 3.3 V level translator
- 3.3 V debug supply block
- J1 temporary Vector breakout header
- J2 6-pin debug/bench header
- Series resistors on monitored Vector-side signals
- Decoupling capacitors
- Test points for UART/I2C/USB/power probing
Key schematic checks pulled during this session showed no ERROR/WARNING/UNCERTAIN issues for:
- ERC floating pins
- ERC power pins
- ERC single-pin nets
- ERC dangling/unconnected wires
- duplicate references
- missing footprints
- parts availability/MPN/datasheet checks queried
- capacitor voltage/decoupling checks queried
PCB Layout
The board has been resized and set up as:
- 80 mm × 60 mm rectangular board
- 2 mm rounded corners
- Standard 2-layer stackup
- Universal keepout enabled
Placement was completed for the debug/interposer topology:
- J1 Vector breakout header placed on the left edge
- J2 debug header placed on the right edge
- ESP32-C3 module placed at the top edge with antenna facing outward
- TXB0104D placed between Vector-side header and ESP/debug side
- Regulator placed near the debug/power side
- Decoupling capacitors placed near the ICs/regulator
- R1–R4 placed between J1 and TXB0104D
- R5 placed near ESP32 EN
- TP1–TP12 arranged as a bottom-edge probe row
Current Blocker
Auto-routing is still blocked by
POSITION_AUTO warnings on hidden/internal Terminal nodes and the U3 regulator sublayout. This appears to be caused by the current +5V to +3V3 LDO Module SOT223 component using an internal sublayout/terminal structure that still reports auto-positioned child nodes even after the visible component is manually placed.The blocker is layout-tool/component-footprint related, not an electrical design blocker.
Recommended Fix
Replace
U3 with a simpler normal schematic/layout component before routing, for example:- A known 3-pin LDO such as AMS1117-3.3/SOT-223, or
- A 3-pin external 3.3 V input header if this debug board is powered from an external 3.3 V bench/USB-serial adapter, or
- A standard Flux regulator part whose footprint does not use nested terminal sublayouts.
After replacing U3:
- Wire input to
DBG_5V_IN, output toDBG_3V3, and ground toGND. - Re-place U3 near J2.
- Re-run route check.
- Run auto-route.
- Re-run airwire/overlap/floating-copper checks.
Important Design Limitation
J1 is still a temporary generic 2.54 mm breakout header. It is not the real Vector connector. The board is useful as a safe debug/probing board, but it is not yet a drop-in Vector brain-board replacement.
Before designing the final brain replacement, the real Vector connector pinout, pitch, mechanical placement, camera/display/audio interfaces, and head/body protocol must be verified by measurement and logic capture.
Current Build Status
Schematic
PCB Layout
Current Blocker
Recommended Fix
Important Design Limitation
