PCB Design Specifications

flux

Confirmed. I’ll now replace the current ARDUINO_EXT with a 9-pin male header, wire pins 1–9 exactly as listed, place it at the bottom-center edge facing downward, update the notes, and re-run review.

flux

I replaced the previous 10-pin J7 ARDUINO_EXT connector with a 9-pin horizontal 2.54 mm male header part as requested.
I was stopped by credit limits immediately after the replacement, so the new J7 still needs to be re-wired and placed. Remaining work:
  • Wire J7:
    • Pin 1 → VBOOST
    • Pin 2 → GND
    • Pin 3 → VDIV1
    • Pin 4 → VDIV2
    • Pin 5 → RGB_R
    • Pin 6 → RGB_G
    • Pin 7 → RGB_B
    • Pin 8 → I2C_SDA
    • Pin 9 → I2C_SCL
  • Place J7 at the bottom-center board edge, opening facing downward.
  • Update the ARDUINO_EXT silkscreen label and Design Notes.
  • Re-run review; existing locked stale routing/unrouted airwire issues were already present before this change.
Wire and place J7
Run ERC/DRC
Update labels and notes
Manual wiring help

Refine this doc
Ask about this doc
Design Notes
Board Setup
  • Board: 100 mm x 100 mm, 2-layer stackup.
  • Top layer: components and routing.
  • Bottom layer: GND copper pour.
  • Edge keepout: 2 mm.
  • Power trace target: 1.5 mm.
  • Signal trace target: 0.3 mm.
  • Minimum clearance: 0.2 mm; 0.5 mm near large storage capacitors.
Input and Rectifier Block
  • J1: PIEZO_INPUT screw terminal, pin 1 = PIEZO_POS, pin 2 = GND.
  • C1: 1 uF, 50 V ceramic input capacitor across PIEZO_POS and GND.
  • D1-D4: 1N5819 Schottky diodes used as the requested rectifier network.
  • RECT_POS: positive rectified output.
  • C2: 470 uF, 25 V bulk storage capacitor from RECT_POS to GND.
  • J2: TP1 test header, pin 1 = RECT_POS, pin 2 = GND.
Cockcroft-Walton Multiplier Block
  • Added a 4-stage multiplier in the center board region (user x=40-65 mm from the left edge, center-origin X -10 mm to +15 mm).
  • Diodes D5-D12: 1N5819 Schottky diodes.
  • Capacitors C3-C10: 10 uF, 25 V aluminum electrolytic capacitors. The user requested C1-C8 for the multiplier, but C1 and C2 were already assigned to the input filter and rectifier bulk capacitor, so the multiplier capacitors are C3-C10 to preserve unique designators.
  • C3-C6 are the series charge capacitor stack; C7-C10 are the shunt transfer/output capacitor stack.
  • MULT_POS is the multiplier positive output.
  • D13 is a 1N5819 protection diode from MULT_POS (anode) to SCAP_IN (cathode) to prevent reverse discharge from the supercapacitor.
  • J3: TP2 test header, pin 1 = MULT_POS, pin 2 = GND.
Supercapacitor Energy Storage Block
  • Added a 2-cell series supercapacitor storage stage in the user x=65-80 mm region (center-origin X +15 mm to +30 mm).
  • C11 = CAP_A: positive to SCAP_IN, negative to SCAP_MID.
  • C12 = CAP_B: positive to SCAP_MID, negative to GND.
  • R1 = 10 kΩ balancing resistor across CAP_A from SCAP_IN to SCAP_MID.
  • R2 = 10 kΩ balancing resistor across CAP_B from SCAP_MID to GND.
  • Combined target per user request: 5.4 V maximum, 0.5 F effective.
  • J4: TP3 test header, pin 1 = SCAP_IN, pin 2 = GND.
  • Silkscreen warning added near the supercapacitors: MAX 5.4V.
Battery Input and MT3608 Boost Module Block
  • J5: BATTERY_INPUT screw terminal block at the left board edge below PIEZO_INPUT. Pin 1 = BAT_IN, pin 2 = GND.
  • BAT_IN is intended for 3.7-4.2 V from TP4056 output positive.
  • J6: 4-pin 2.54 mm male header used as the MT3608 boost converter module interface. Pin 1 = IN+ / BAT_IN, pin 2 = IN- / GND, pin 3 = OUT+ / VBOOST, pin 4 = OUT- / GND.
  • VBOOST is the regulated 5 V output from the external MT3608 module.
  • C13 = C_BOOST: 100 nF, 50 V ceramic decoupling capacitor from VBOOST to GND placed beside the boost output header.
  • Silkscreen warning near the boost header: SET TRIMMER TO 5V BEFORE USE.
  • Power-budget caveat: downstream VBOOST load current is not specified yet. For boost converters, input current must be calculated with the lowest battery voltage using I_in = (V_out x I_out) / (V_in_min x efficiency). BAT_IN trace/current sizing should be revisited when the 5 V load is known.
Arduino ADC Voltage Divider Block
  • J7: ARDUINO_EXT 10-pin 2.54 mm header for Arduino analog and I2C sensing. Pin 3 = VDIV1, pin 4 = VDIV2, pin 8 = I2C_SDA, pin 9 = I2C_SCL. Pins 1, 2, 5, 6, 7, and 10 are reserved/unassigned and marked no-connect.
  • VDIV1 supercapacitor voltage sense: R3 = 10 kΩ from SCAP_IN to VDIV1, R4 = 47 kΩ from VDIV1 to GND, and VDIV1 connects to J7 pin 3.
  • VDIV1 scaling: VOUT = VIN x 47 kΩ / (10 kΩ + 47 kΩ). At SCAP_IN = 5.4 V, VDIV1 ≈ 4.45 V for safe Arduino ADC reading when using a 5 V ADC reference.
  • VDIV2 live generation sense: R5 = 10 kΩ from RECT_POS to VDIV2, R6 = 47 kΩ from VDIV2 to GND, and VDIV2 connects to J7 pin 4.
  • Silkscreen labels added: ARDUINO_EXT, VDIV1, and VDIV2.
OLED Display Headers
  • J8: OLED_096 / I2C 0x3C / LIVE GENERATION 4-pin female header at the upper-right board edge. Pin 1 = VBOOST, pin 2 = GND, pin 3 = I2C_SDA, pin 4 = I2C_SCL.
  • C14: 100 nF local decoupling capacitor from VBOOST to GND placed at J8.
  • J9: OLED_13 / I2C 0x3D / ENERGY STORED 4-pin female header stacked below J8 on the right side. Pin 1 = VBOOST, pin 2 = GND, pin 3 = I2C_SDA, pin 4 = I2C_SCL.
  • C15: 100 nF local decoupling capacitor from VBOOST to GND placed at J9.
  • J8 and J9 share I2C_SDA and I2C_SCL through ARDUINO_EXT pins 8 and 9.
  • Silkscreen note added near J9: BRIDGE BACK JUMPER TO SET 0x3D.
  • Reminder: OLED modules commonly include I2C pull-ups; if neither OLED module nor Arduino carrier provides pull-ups, add one 4.7 kΩ pull-up pair from SDA/SCL to the logic rail used by the Arduino I2C interface.
Notes
  • The requested bridge list named D4 anode as PIEZO_NEG, but the input connector defined pin 2 as GND and did not provide a separate PIEZO_NEG terminal. D4 anode is therefore tied to GND in this implementation.
  • Electrolytic capacitor polarities in the Cockcroft-Walton ladder were oriented so each positive terminal connects to the higher-potential/lifted stage node and each negative terminal connects to the lower-potential node or GND.
  • Exact 2.7 V 1 F supercapacitor parts were not found in the available library. The layout uses available 1 F EDLC parts with higher per-device voltage rating as placeholders while preserving the requested 5.4 V system warning and series stack topology.

  • Board Setup

  • Input and Rectifier Block

  • Cockcroft-Walton Multiplier Block

  • Supercapacitor Energy Storage Block

  • Battery Input and MT3608 Boost Module Block

  • Arduino ADC Voltage Divider Block

  • OLED Display Headers

  • Notes

Documents

Assets

Assets are files uploaded to this project which can be used in various ways.

Thermo-Acoustic Generator PCB thumbnail
100 mm × 100 mm two-layer thermo-acoustic generator PCB with top-side components/traces, bottom GND pour, M3 mounting holes, keepouts, and title silkscreen.

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Controls