U3 to IC1 Transfer

Thought for 1 min 36 sec
Reading TPS63802 Stage 2 Verification's report…
Thought for 14 sec
3/3 Verify capacitor evidence, touched-net diffs, ERC, and all negative checks independently

Phase A: verify Stage 1 state, exact-part availability, and TPS63802 footprint geometry

Phase B: replace L3, add and wire U3, and add feedback divider

Verify capacitor evidence, touched-net diffs, ERC, and all negative checks independently

Thought for 7 sec
Awaiting 1 background task
Received notification from "TPS63802 Audit" that it finished — picking the work back up.

flux

Stage 2 build is complete:
  • U3 TPS63802DLAT installed and wired
  • L3 replaced with Murata DFE201612E-R47M=P2
  • R13/R25 feedback divider added
  • Critical switch nodes reported correctly separated: U3 pin 7/L3 pin 2=REG_SW2; U3 pin 9/L3 pin 1=REG_SW1
  • PG is explicitly unconnected; PGOOD_N unchanged
  • Initial ERC reported clean
The independent audit finished, but I cannot retrieve and reconcile its final report because no ACUs remain. That reconciliation, the full 12-item report, and final Stage 2 sign-off remain pending; no further project changes should be made until the audit is reviewed.
Reconcile the TPS63802 audit
Review remaining design checks
Verify regulator implementation
Document Stage 2 decisions
Sign up to send

Files

Schematic

Layout

Preview

ENC1
R13
Resistance
Resistance
L3
Inductance
Inductance
U1
J2
D1
R25
Resistance
Resistance
Project Specification
Project Overview
  • Status: Schematic implemented and reviewed
  • Compact battery-powered ESP32-S3 rotary UI controller with native USB-HID, BLE/Wi-Fi, USB-C charging/power path, a user-approved pressable 24-detent encoder, conventional PWM RGB feedback, and a disconnectable power indicator.
Intended Use
  • Compact prototype control knob for media, smart-home, and machine-parameter applications.
  • Operates over native USB-HID or wirelessly; supports USB-only flashing.
Main Features
  • ESP32-S3-WROOM-1-N8 integrated-antenna module.
  • USB-C USB 2.0 sink/device with USBLC6-2SC6 ESD and independent 5.1 kΩ CC pull-downs.
  • BQ24074 power-path charger, USB500 mode, ~300 mA charge current, battery-absent operation.
  • TPS63001 fixed 3.3 V buck-boost with FXL0530-2R2-M power inductor.
  • Bourns PEC11R-4220F-S0024 24-detent/24-pulse encoder with push switch; the detented behavior is explicitly accepted and supersedes the original non-detented preference.
  • Kingbright APFA3010LSEKJ3ZGKQBC common-cathode RGB LED with independent active-high PWM channels.
  • ROHM SML-D13FWT86C green 3V3 power LED with normally closed JP1 disable solder bridge.
System Architecture
Diagram



  
    
  
  
    
  























USB-C VBUS + USB 2.0
USB ESD + 22 ohm series resistors
ESP32-S3-WROOM-1-N8
BQ24074 power path
Protected node_1S LiPo
SYS / OUT
TPS63001 3.3 V buck-boost
Common-cathode RGB LED via R/G/B resistors
24-detent encoder + push
NC power-LED jumper
Low-current green power LED
Hardware Subsystems
  • Compute/RF: ESP32-S3-WROOM-1-N8, 8 MB flash, integrated antenna.
  • Power: BQ24074 charger/power path and TPS63001 3.3 V buck-boost.
  • Input: PEC11R-4220F-S0024; A/B firmware debounce and 1 ms RC on active-low push.
  • RGB status: APFA3010LSEKJ3ZGKQBC common cathode. Red GPIO7 through 510 Ω; green GPIO8 through 220 Ω; blue GPIO15 through 220 Ω. Active-high PWM.
  • Power status: 3V3 → normally closed JP1 → 3 kΩ → SML-D13FWT86C → GND, approximately 0.4 mA. JP1 is opened by cutting or solder wicking.
Interfaces and GPIO Map

Table

FunctionGPIONotes
Encoder press4RTC-capable active-low wake
Encoder A5Input
Encoder B6Input
RGB red7Active-high PWM
RGB green8Active-high PWM
RGB blue15Active-high PWM
Charger CHG_N9Active-low input
PGOOD_N10Active-low input
USB D−19Native USB
USB D+20Native USB
BOOT0Strap/button only
GPIO7/8/15 are non-strapping GPIOs and are not reserved for flash/PSRAM on the N8 module variant.
Power Budget

Table

LoadDesign peak
ESP32-S3 radio transient500 mA at 3.3 V
PWM RGB LED~9 mA typical with all channels on
Power LED~0.4 mA while JP1 is closed
3.3 V rail target600 mA transient minimum
At 3.0 V battery and 90% efficiency, a 600 mA load at 3.3 V reflects to about 0.733 A battery current. The status LEDs do not materially change regulator sizing.
Manufacturing and Assembly
  • JLCPCB prototype assembly; four-layer JLC7628 is the later layout target.
  • All BOM components have MPNs and footprints. JP1 is a validated default-bridged two-pad solder-jumper footprint and is intentionally excluded from the assembly BOM.
  • Power-indicator silkscreen/layout should identify JP1 as POWER LED DISABLE — CUT/OPEN.
Firmware Requirements
  • PWM outputs are active high because LED1 is common cathode.
  • Drive GPIO7, GPIO8, and GPIO15 low before deep sleep to turn RGB off.
  • Encoder A/B debounce is in firmware; push remains active-low wake on GPIO4.
Important Design Decisions
  • Existing PEC11R-4220F-S0024 detented encoder retained by explicit user approval.
  • Addressable RGB circuitry removed in favor of direct, low-current three-channel PWM.
  • Power LED current is minimized and can be physically disconnected with JP1.
Assumptions
  • Protected LiPo cutoff is near 3.0 V.
  • No USB-PD or Type-C current-advertisement detection.
  • Formal compliance qualification is outside prototype scope.
Change Notes
  • Final encoder/RGB/power-indicator correction implemented.
  • Final schematic contains 49 components and 37 nets; JP1 is excluded from the assembly BOM, yielding 48 BOM instances.
  • ERC, BOM, MPN, footprint, passive, and sourcing checks re-run after changes.
  • Eight residual schematic warnings are cosmetic auto-generated portal-label overlaps only.

  • Project Overview

  • Intended Use

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Interfaces and GPIO Map

  • Power Budget

  • Manufacturing and Assembly

  • Firmware Requirements

  • Important Design Decisions

  • Assumptions

  • Change Notes