BLE RGB LED Board

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Routing was partially completed: the D1→D32 LED data chain is routed, plus several support/control nets including level-shifter LED data, charger ISET/ILIM/TMR, BAT_NTC, CHG_STAT_N, and USB-C CC/ESD connections.
Open items:
  • The board is not fabrication-ready yet.
  • 88 airwire issues remain, mainly power distribution and blocked control/debug routes.
  • The compact charger/battery/power area needs either a full-board autorouter pass or small placement cleanup.
  • Key unrouted items include BAT_PLUS, VBUS, SYS, LED_VDD, 3V3/GND strategy, LED_EN, RESET_N, PGOOD_N, SWD reroute, USB D+/D− reserved ESD lines, and antenna-related copper details.
  • I updated Layout Plan with the partial routing status.
Suggested next steps:
  1. Slightly spread U2/J2/U5/U3 power area and rerun routing.
  2. Route power with wider copper/pours rather than skinny traces.
  3. Re-route SWD/reset cleanly.
  4. Run full DRC after the next routing pass.
S

sullys

keep working til it's finished please

flux

I’ll keep going: first I’ll open up the congested power/charger area, then continue routing remaining power, debug, reset, and status nets, with checks after each cleanup pass.

flux

I’m blocked now because the account has no available ACUs, so I can’t continue executing layout/routing actions.
Accomplished in this session:
  • Re-checked the routing state and confirmed the main blocker is still the tight charger/battery area around U2/J2.
  • Removed leftover conflicting SWD trace segments that were causing copper-overlap problems.
  • Expanded the board from 80×40 mm to 90×42 mm to improve routing space and reduce density.
Open items:
  • Re-place/spread U2, J2, R5/R7/R8/R9, U3, U5, and nearby passives into the new extra space.
  • Continue routing remaining airwires, especially BAT_PLUS, VBUS, SYS, LED_VDD, 3V3/GND, LED_EN, RESET_N, PGOOD_N, SWD, and USB D+/D− reserved/ESD lines.
  • Run DRC after routing and clean any remaining conflicts.
  • Update the Layout Plan after the next completed routing pass.
Check ACUs
List routing blockers
Suggest charger placement
Run DRC
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Files

Schematic

Layout

Preview

Board Bring-Up Plan — BLE RGB LED Display
Prerequisites
  • Tools: current-limited bench supply, multimeter, oscilloscope, SWD programmer, thermometer/thermal camera if available.
  • Firmware: see Firmware Starter after pin mapping is confirmed.
  • Safety: do not connect an unverified LiPo pack; first power the board from a current-limited supply with LED_EN forced off.
1. Visual Inspection
  • Verify U1 ANNA-B112 orientation and antenna area.
  • Verify U2 BQ24074 exposed pad and pin-1 orientation.
  • Verify J1 USB-C shell solder and VBUS/GND pins.
  • Verify J2 battery connector polarity: BAT_PLUS, BAT_NTC, GND.
  • Verify all 32 SK6812MINI-E LED orientations in the data-chain direction.
2. Power Rail Verification

Table

RailSourceExpectedMeasure atInitial current limitPass criteria
VBUSUSB-C / bench supply5.0 VJ1/U2 VBUS20-30 mA first rampNo shorts/heating.
SYSBQ24074 OUT/SYS~VBUS-derived or BAT-derived SYSU2 OUT/SYS, U3 IN, U5 IN50-100 mA early testStable and not shorted.
3V3TPS782333.3 VU3 OUT, U1 VDD50-100 mA3.3 V within regulator tolerance.
BAT_PLUSBattery connector / charger BAT0-4.2 V depending setupJ2 pin and U2 BATbattery simulator preferredCorrect polarity and charger behavior.
LED_VDDMP5075 outputOff at boot; SYS when enabledU5 OUT, D1/D32 VDDtest with dummy load firstNo unexpected enable or excessive droop.
3. First-Power Procedure
  1. Leave battery disconnected.
  2. Set bench supply to 0 V with 20-30 mA limit into VBUS.
  3. Ramp to 5 V while monitoring current.
  4. Confirm 3V3 is present and LED_VDD remains off.
  5. Check U2/U3/U5 for heating.
  6. Connect SWD and confirm the module can be detected.
4. Charger and Battery Tests
  1. Use a battery simulator or protected test fixture before a real cell.
  2. Sweep BAT_PLUS from depleted through 4.2 V.
  3. Verify charge current, input current limit, termination/recharge, and thermal behavior.
  4. Test BAT_NTC normal, open, short, hot, and cold cases.
  5. Only then test with the approved protected LiPo pack.
5. LED Rail Tests
  1. Test U5 LED_VDD with a resistor/electronic dummy load first.
  2. Verify LED_EN defaults low through reset, SWD attach, firmware crash, and power cycling.
  3. Enable one-pixel/low-brightness firmware pattern.
  4. Step through 1, 4, 8, 16, and 32 pixels.
  5. Measure BAT_PLUS, SYS, LED_VDD, 3V3, total current, and component temperatures.
  6. Time-limit full-white testing and only do it with instrumentation.
6. BLE Functional Validation

Table

TestExpected result
BLE advertisingDevice advertises as BLE RGB Display or selected product name.
BLE connectionSmartphone or test central connects reliably.
Display commandBrightness/animation changes without rail brownout.
Low batteryFirmware dims or disables LEDs before unreliable operation.
Charging while activeNo overheating; charging behavior is documented.
7. RF / Antenna Checks
  • Confirm final ANNA-B112 antenna orientation, carrier-board tuning geometry, and keepout.
  • Keep copper, traces, vias, battery, and metal away from the antenna zone per u-blox guidance.
  • Test BLE range with USB attached and detached, and with the final battery installed.
8. Pass/Fail Summary

Table

SectionResultNotes
Visual inspection[ ] Pass / [ ] Fail
Power rails[ ] Pass / [ ] Fail
Charger/battery[ ] Pass / [ ] Fail
SWD programming[ ] Pass / [ ] Fail
LED rail[ ] Pass / [ ] Fail
BLE function[ ] Pass / [ ] Fail
RF/antenna[ ] Pass / [ ] Fail
Open Items Before Ordering Boards
  • Final compact placement and routing.
  • Antenna keepout/tuning implementation.
  • Battery pack approval and connector polarity verification.
  • Hardware LED current-limit decision.
  • DRC/ERC review with all airwires resolved.

  • Prerequisites

  • 1. Visual Inspection

  • 2. Power Rail Verification

  • 3. First-Power Procedure

  • 4. Charger and Battery Tests

  • 5. LED Rail Tests

  • 6. BLE Functional Validation

  • 7. RF / Antenna Checks

  • 8. Pass/Fail Summary

  • Open Items Before Ordering Boards