# #4 AI Context Consensus Processor (ACCP) ## Description PCIe Gen4 x16 Subsystem for ACCP 2U Blade: Integrated Switch, Lane Bifurcation, and SRNS Refclk with 85Ω Impedance Routing ## Project Details - **Owner:** sucoro - **Created:** 10/28/2025 - **Last Updated:** 10/29/2025 - **Visibility:** Public - **Stackup:** Standard 10 Layer - **Pending_Violations:** No ERC or DRC issues detected - **GND_Stitching_Pitch:** 5 mm along the defined keepout boundaries - **Board Width:** 482.6mm - **Bus Type:** PCIe 4.0 - **Last_Route_Validation:** 2025-10-29T00:00:00Z - **Stackup:** Standard 4 Layer - **Pair to Pair Skew Max:** 20ps - **Net Type:** High Speed - **Power Planes:** Inner Layers 2 and 3 - **high_speed_keepout_and_stitching:** Upstream domain: 0.5 mm keepout margin around PCIe Gen4 x16 lane routing regions; Downstream domains: 0.5 mm keepout margin around x8 fanout regions; Stitching vias every 5 mm along differential pair return‐path boundaries. - **Upstream_Keepout_Boundaries:** 0.5 mm keepout margin around x16 upstream PCIe lane routing area - **Controlled Impedance:** 85Ω - **Downstream_Keepout_Boundaries:** 0.5 mm keepout margin around x8 downstream fan-out routing area - **Board Height:** 88.9mm - **Ground Fill Layers:** Top and Bottom - **SRNS_refclk_net_class:** differential pair ~85 Ω, skew ≤2 ps, length matching ±50 mil, dedicated routing. - **Min Differential Pair Spacing:** 6mil - **PCIE_Lanes_NetClass:** target impedance: 85Ω; min spacing: 6 mil; max PN skew: 5 ps; max pair-to-pair skew: 20 ps; max vias per lane: 2 - **Downstream_Keepout_Region:** 0.5 mm keepout around x8 downstream fan-out routing area - **Upstream_Keepout_Region:** 0.5 mm keepout around x16 upstream PCIe lane routing area - **PN Skew Max:** 5ps - **System Architecture:** ``` mermaid graph TD CE["PCIe x16 Card-edge Connector"] -->|"16x PCIe Gen4 Lanes + SRNS REFCLK + Sideband + Power (12V, 3.3V_AUX)"| SW["PCIe Gen4 Switch (x16 Upstream)"] SW -->|"x8 PCIe Gen4 Lanes + Sidebands + Power"| EP1["Downstream x8 Endpoint Connector #1"] SW -->|"x8 PCIe Gen4 Lanes + Sidebands + Power"| EP2["Downstream x8 Endpoint Connector #2"] CE -.->|"Sideband: PERST#, CLKREQ#, WAKE#, SMBus/PD, Presence Detect"| SW CE -.->|"Power: 12V, 3.3V_AUX"| SW ``` - **Differential Coupling:** enabled - **Max Vias Per Lane:** 2 - **SRNS_REFCLK_NetClass:** target impedance: 85Ω; skew ≤ 2 ps; length matching ±50 mil; dedicated differential routing; max vias: 2 ## Key Components ### J1 — [APCI0164-P001A](https://www.flux.ai/lcsc/apci0164-p001a.md) - Part Type: Card Edge Connectors - JLCPCB Part Class: Extended Part - Datasheet URL: https://storage.googleapis.com/graviton-electric-symbols/document_assets/lcsc/2012071238_LOTES-APCI0164-P001A_C841666.pdf - position: {"x": -241.3, "y": 7.5} - Package or Case Code: PCI-SMD_APCI0164-P001A - Manufacturer Part Number: APCI0164-P001A - Role Details: PCIe x16 card-edge connector - LCSC Part Number: C841666 - Manufacturer Name: 嘉澤端子(LOTES) - Product Info Url: https://lcsc.com/product-detail/Card-Edge-Connectors_LOTES-APCI0164-P001A_C841666.html **Pins:** - 1 [pin 1] - 10 [pin 10] - 11 [pin 11] - 12 [pin 12] - 13 [pin 13] - 14 [pin 14] - 15 [pin 15] - 16 [pin 16] - 17 [pin 17] - 18 [pin 18] - 19 [pin 19] - 2 [pin 2] - 20 [pin 20] - 21 [pin 21] - 22 [pin 22] - 23 [pin 23] - 24 [pin 24] - 25 [pin 25] - 26 [pin 26] - 27 [pin 27] - 28 [pin 28] - 29 [pin 29] - 3 [pin 3] - 30 [pin 30] - 31 [pin 31] - 32 [pin 32] - 33 [pin 33] - 34 [pin 34] - 35 [pin 35] - 36 [pin 36] - 37 [pin 37] - 38 [pin 38] - 39 [pin 39] - 4 [pin 4] - 40 [pin 40] - 41 [pin 41] - 42 [pin 42] - 43 [pin 43] - 44 [pin 44] - 45 [pin 45] - 46 [pin 46] - 47 [pin 47] - 48 [pin 48] - 49 [pin 49] - 5 [pin 5] - 50 [pin 50] - 51 [pin 51] - 52 [pin 52] - 53 [pin 53] - 54 [pin 54] - 55 [pin 55] - 56 [pin 56] - 57 [pin 57] - 58 [pin 58] - 6 [pin 6] - 67 [pin 67] - 68 [pin 68] - 69 [pin 69] - 7 [pin 7] - 70 [pin 70] - 71 [pin 71] - 72 [pin 72] - 73 [pin 73] - 74 [pin 74] - 75 [pin 75] - 76 [pin 76] - 8 [pin 8] - 9 [pin 9] ### U1 — [PI3PCIE3412AZHEX](https://www.flux.ai/adrian95/pi3pcie3412azhex.md) - Part Type: Integrated Circuit - Role: Switching - position: {"x":-236.3,"y":7.5} - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://www.diodes.com/assets/Datasheets/PI3PCIE3412A.pdf - Manufacturer Part Number: PI3PCIE3412AZHEX - Role Details: PCIe Gen4 x16→2×x8 switch - Manufacturer Name: Diodes Incorporated **Pins:** - A0- [pin 3] - A0+ [pin 2] - A1- [pin 7] - A1+ [pin 6] - A2- [pin 12] - A2+ [pin 11] - A3- [pin 16] - A3+ [pin 15] - B0- [pin 37] - B0+ [pin 38] - B1- [pin 35] - B1+ [pin 36] - B2- [pin 28] - B2+ [pin 29] - B3- [pin 26] - B3+ [pin 27] - C0- [pin 33] - C0+ [pin 34] - C1- [pin 31] - C1+ [pin 32] - C2- [pin 24] - C2+ [pin 25] - C3- [pin 22] - C3+ [pin 23] - EP [pin 43] - GND_1 [pin 1] - GND_2 [pin 4] - GND_3 [pin 10] - GND_4 [pin 14] - GND_5 [pin 17] - GND_6 [pin 19] - GND_7 [pin 21] - GND_8 [pin 39] - GND_9 [pin 41] - SEL [pin 9] - V_DD_1 [pin 5] - V_DD_2 [pin 18] - V_DD_3 [pin 20] - V_DD_4 [pin 40] - V_DD_5 [pin 42] - VDD_1 [pin 8] - VDD_2 [pin 13] - VDD_3 [pin 30] ### U2 — [LTC6957IDD-1#PBF](https://www.flux.ai/lcsc/ltc6957idd-1pbf.md) - Part Type: Clock Buffers, Drivers - Package or Case Code: DFN-12_L3.0-W3.0-P0.45-BL-EP - Product Info Url: https://lcsc.com/product-detail/Pre-ordered-Products_Analog-Devices_LTC6957IDD-1-PBF_Analog-Devices-ADI-LINEAR-LTC6957IDD-1-PBF_C689876.html - Datasheet URL: https://assets.lcsc.com/datasheet/szlcsc/Download-ISO9001-Certification.pdf - Role Details: PCIe reference clock buffer - Manufacturer Name: ADI(亚德诺)/LINEAR(凌特) - JLCPCB Part Class: Extended Part - Role: Signal Generation - Manufacturer Part Number: LTC6957IDD-1#PBF - position: {"x": -221.3, "y": 7.5} - LCSC Part Number: C689876 **Pins:** - EP [pin 13] - FILTA [pin 1] - FILTB [pin 6] - GND [pin 5] - IN– [pin 4] - IN+ [pin 3] - OUT1– [pin 10] - OUT1+ [pin 11] - OUT2– [pin 9] - OUT2+ [pin 8] - SD1 [pin 12] - SD2 [pin 7] - V+ [pin 2] ### U3 — [TUSB1046-DCIRNQT](https://www.flux.ai/adrian95/tusb1046-dcirnqt.md) - Role Details: PCIe Gen4 retimer (optional) - Reserved Keepout Margin: 5mm - Part Type: Integrated Circuit - Role: Signal Generation - Manufacturer Name: Texas Instruments - License: https://creativecommons.org/licenses/by/4.0/ - Datasheet URL: https://www.ti.com/lit/ds/symlink/tusb1046-dci.pdf - Manufacturer Part Number: TUSB1046-DCIRNQT **Pins:** - AUXN [pin 25] - AUXP [pin 24] - CAD_SNK/RSVD1 [pin 29] - CTL0/SDA [pin 22] - CTL1/HPDIN [pin 23] - DP0N [pin 10] - DP0P [pin 9] - DP1N [pin 13] - DP1P [pin 12] - DP2N [pin 16] - DP2P [pin 15] - DP3N [pin 19] - DP3P [pin 18] - DPEQ0/A1 [pin 14] - DPEQ1 [pin 2] - EP_(GND) [pin 41] - EQ0 [pin 38] - EQ1 [pin 35] - FLIP/SCL [pin 21] - HPDIN/RSVD2 [pin 32] - I2C_EN [pin 17] - RX1N [pin 31] - RX1P [pin 30] - RX2N [pin 39] - RX2P [pin 40] - SBU1 [pin 27] - SBU2 [pin 26] - SSEQ0/A0 [pin 11] - SSEQ1 [pin 3] - SSRXN [pin 4] - SSRXP [pin 5] - SSTXN [pin 7] - SSTXP [pin 8] - TX1N [pin 34] - TX1P [pin 33] - TX2N [pin 36] - TX2P [pin 37] - VCC_1 [pin 1] - VCC_2 [pin 6] - VCC_3 [pin 20] - VCC_4 [pin 28] ### Y1 — [CCSS-945X-25-100.000](https://www.flux.ai/adrian95/ccss-945x-25-100p000.md) - Role: Signal Generation - Datasheet URL: https://www.crystek.com/crystal/spec-sheets/clock/CCSS-945.pdf - Part Type: Oscillator - Role Details: 100 MHz SRNS reference clock source - License: https://creativecommons.org/licenses/by/4.0/ - Manufacturer Part Number: CCSS-945X-25-100.000 - position: {"x":-226.3,"y":7.5} - Manufacturer Name: Crystek Corporation **Pins:** - GND - NC - OUT - VDD *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/sucoro/4-ai-context-consensus-processor-accp](https://www.flux.ai/sucoro/4-ai-context-consensus-processor-accp).* --- *Generated from [https://www.flux.ai/sucoro/4-ai-context-consensus-processor-accp](https://www.flux.ai/sucoro/4-ai-context-consensus-processor-accp)*