W00c0n Badge Production
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w00c0n 30 badge — RED top board production export
Production-intent two-board clamshell badge for w00c0n 30th anniversary: red top art board with inward-facing addressable LEDs and black bottom electronics/art board for JLCPCB turnkey assembly.
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w00c0n 30 badge — BLACK bottom board production export
Production-intent two-board clamshell badge for w00c0n 30th anniversary: red top art board with inward-facing addressable LEDs and black bottom electronics/art board for JLCPCB turnkey assembly.
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RED board production completion/export
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BLACK board production completion/export
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I’m blocked now because the account has no available ACUs, so I can’t continue executing tools or wait on the spawned board-completion threads.
Accomplished so far:
- Updated production docs to make the coin-cell/WS2812 voltage, runtime, firmware-cap, P-MOS fault-scope, and one-cell-reversed risks explicit blockers: Production Release Risk Review.
- Re-sourced/updated BOM metadata for the JLCPCB/LCSC parts and documented the audit: JLCPCB BOM Sourcing Audit.
- Updated the firmware, bring-up, stackup/alignment, project specification, and blocker notes with low-battery, validation, and per-board export side/orientation gates.
- Cloned the master into separate RED and BLACK production-export projects and started board-specific completion/export threads, but those did not finish before ACUs became unavailable.
Open items:
- Finish the RED and BLACK board-specific layout/export threads.
- Apply/import artwork and shared outline, or document exact tooling blockers.
- Place aligned standoff holes and correct component sides.
- Route both boards, run/fix ERC/DRC, and export separate JLCPCB Gerber/drill/BOM/CPL packs.
- Validate the CR2032/WS2812 voltage/runtime and parallel-cell fault behavior before any production-ready claim.
Manual export steps
Validation checklist
JLCPCB file list
Production warning notes
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Production Release Risk Review — Coin Cells and JLCPCB Export Gates
Date: 2026-07-11
Status: Production claim blocked until validation evidence is recorded
Summary
Independent review identified release risks that must be treated as production blockers, not cosmetic warnings. The current architecture may be preserved only if the badge brief requires two CR2032 coin cells and no larger battery/regulator architecture, but the design must not be represented as production-ready until electrical validation confirms acceptable voltage margin, runtime, thermal/current behavior, and user-replaceable-cell fault behavior.
Production Blocking Risks
1. WS2812B-2020 on direct 2x CR2032 rail is marginal
- The LED rail is a direct coin-cell rail after switch and P-MOS reverse-polarity stage.
- WS2812B-family LEDs are specified around a higher nominal supply than a sagging coin-cell rail; operation near 3 V can work in practice but is not guaranteed across vendors, temperature, aging, LED bins, and dynamic current pulses.
- At the documented firmware cap target of about 63 mA total, two CR2032 cells in parallel are operating well above the low-drain conditions where their nominal capacity is specified.
- Voltage sag and internal resistance can cause color shift, flicker, resets, or LED data-chain failures before nominal cell capacity is consumed.
Production gate: Validate with assembled prototypes using fresh, mid-life, and near-depleted matched cells at room and expected event temperatures. Record minimum VLED at the first LED and MCU VDD during worst-case animation current pulses.
2. Parallel user-replaceable coin cells need fault analysis
- Directly paralleled user-replaceable coin cells can cross-charge if cells are mismatched in type, age, voltage, chemistry, or orientation.
- The existing single upstream P-MOS reverse-polarity stage protects the downstream circuit from a fully reversed battery rail, but it does not inherently isolate one coin cell from the other if one cell is inserted reversed while the other is inserted correctly.
- A one-cell-reversed fault can create a cell-to-cell current path through the holders/parallel connection before the load-side reverse-protection device can help.
Production gate: Either add per-cell isolation/current limiting/ideal-diode analysis, or document that cells must be factory-installed/matched and not user-replaceable. Validate/measure worst-case one-cell-reversed current if the physical product allows user replacement.
3. Firmware current cap is not a hardware safety mechanism
- Firmware brightness limits are required for usability and runtime, but firmware can fail, be reflashed, hang, or run test code.
- A firmware cap cannot be the only basis for a production safety or source-current claim.
Production gate: Production notes and marketing/release language must not claim safe/high-confidence runtime or current limit solely from firmware. Hardware/source limitations and validation data must support the final claim.
4. P-MOS reverse protection scope must be explicit
- The P-MOS reverse-polarity device should be verified for normal drop at the intended current and for load-side reverse protection behavior.
- It should not be assumed to protect against per-cell mismatch or one reversed cell in a direct parallel-cell architecture.
Production gate: Bring-up must include polarity/fault review and measured voltage drop across the P-MOS at representative current.
5. Separate per-board JLCPCB exports must be independently checked
- Red/top and black/bottom boards require separate fabrication packages because mask color, artwork, component sides, and assembly content differ.
- Side/orientation must be checked visually in a Gerber viewer and against CPL origin/rotation before JLCPCB assembly.
Production gate: Export separate Gerber/drill/BOM/CPL packs for each board and record viewer checks for: board outline dimensions, artwork layer side, no components on visible faces, LED underside orientation, bottom-back electronics side, standoff hole alignment, and connector pinout.
Required Firmware Requirements Before Production
- Enforce low-brightness default; no full-white or high-brightness production mode.
- Implement low-battery behavior: reduce brightness and/or shut down animation when VLED falls below a validated threshold.
- If ATtiny1614 ADC is available on the direct rail, add a calibrated VDD or VLED measurement method suitable for this architecture.
- Add startup self-test that avoids simultaneous full-bright white on all LEDs.
- Preserve a hard-coded maximum brightness/current cap in production firmware and document the exact release binary/hash.
Conservative Runtime Position
Until measured prototypes exist, state runtime as validation pending. A conservative engineering expectation for the existing 2x CR2032 direct-rail approach is that visible operation may be only a few hours at sustained capped load, with brightness and color reliability degrading as cells sag. Runtime claims must be based on measured current waveform and cutoff behavior, not nominal CR2032 mAh alone.
Architecture Decision
Current architecture may continue only if the badge brief requires coin cells and the thin clamshell form factor. If production reliability is prioritized over strict brief preservation, recommended alternatives are:
- Single LiPo or primary lithium cell with suitable holder/protection, if allowed mechanically and by event rules.
- Per-cell ideal-diode or Schottky isolation for CR2032s, accepting voltage-drop/runtime tradeoffs.
- Fewer LEDs, lower LED count population option, or non-addressable low-current LEDs.
- Add a hardware current-limiting element if fault analysis requires it.
Release Checklist Addendum
- VLED sag measured at MCU and LED1 under worst-case production animation.
- LED chain behavior validated over expected coin-cell voltage range.
- Parallel-cell fault analysis completed; one-cell-reversed case explicitly addressed.
- P-MOS voltage drop and reverse-protection scope verified.
- Production firmware includes low-battery brightness reduction/shutdown.
- Firmware release binary/hash recorded.
- Separate red-board and black-board JLCPCB packages exported and visually checked.
- BOM/CPL sides/orientations checked for each board independently.
Current Manufacturing Readiness Statement
Not production-ready yet. The project may continue toward JLCPCB turnkey output, but final production release is blocked until layout/export blockers are cleared and the power/fault-validation gates above are satisfied.
Summary
Production Blocking Risks
1. WS2812B-2020 on direct 2x CR2032 rail is marginal
2. Parallel user-replaceable coin cells need fault analysis
3. Firmware current cap is not a hardware safety mechanism
4. P-MOS reverse protection scope must be explicit
5. Separate per-board JLCPCB exports must be independently checked
Required Firmware Requirements Before Production
Conservative Runtime Position
Architecture Decision
Release Checklist Addendum
Current Manufacturing Readiness Statement
