# [2-layer] JLCPCB Constraints cBsU ## Description Use this template if you're planning to get your 1 to 2-layer board manufactured in JLCPCB. It has the via min/max and trace width constraints already baked as global rules. #project-template #template #manufacturer-design-rules ## Project Details - **Owner:** spurgazr - **Created:** 10/16/2024 - **Last Updated:** 10/16/2024 - **Visibility:** Public ## Key Components ### U1 — [IP5328P](https://www.flux.ai/jecstronic/ip5328p~xk5.md) - Manufacturer Part Number: IP5328P - Part Type: Integrated Circuit **Pins:** - AGND - BAT - BST - CC1 - CC2 - DBP - DMA1 - DMA2 - DMB - DMC - DPA1 - DPA2 - DPC - EPAD - KEY - L1 - L2 - L3 - LIGHT - LX - LX - LX - LX - LX - NTC - RSET - VBUS - VBUSG - VIN - VING - VOUT1 - VOUT1G - VOUT2 - VOUT2G - VREG - VSN - VSP - VSYS - VSYS - VSYS3 - VSYS4 *The full schematic, PCB layout, bill of materials, and interactive design are available at [https://www.flux.ai/spurgazr/2-layer-jlcpcb-constraints-cbsu~tn](https://www.flux.ai/spurgazr/2-layer-jlcpcb-constraints-cbsu~tn).* --- *Generated from [https://www.flux.ai/spurgazr/2-layer-jlcpcb-constraints-cbsu~tn](https://www.flux.ai/spurgazr/2-layer-jlcpcb-constraints-cbsu~tn)*