• Status: Approved for Phase 1 prototype design
• 200–240 MHz to 10.7 MHz double-conversion CW receiver front end.
• Both local oscillators are external SMA inputs; no on-board synthesis.

• Bench-validation prototype for the electrical architecture while preserving previously calculated inter-stage geometry.
• External LO1 is 245–285 MHz; external LO2 is 34.3 MHz square wave.

• Accept a 200–240 MHz antenna signal and produce a 10.7 MHz IF output.
• Provide approximately 25 dB cascade gain and approximately 2.5 dB noise figure.
• Support narrowband CW sensitivity in the approximate −136 to −144 dBm range for 500–100 Hz detection bandwidth.

• HMC8410 low-noise RF input stage and 5-pole 200–240 MHz BPF.
• ADE-1+ dual conversion: RF to 45 MHz, then 45 MHz to 10.7 MHz.
• External LO1 and LO2 SMA inputs; mandatory LO2 harmonic low-pass filter.
• GALI-74+ amplifiers at both IFs with complete bias and DC-block networks.
• 5 V RF rail, 3.3 V auxiliary rail, and sequenced negative gate bias.

Diagram

• RF input: edge-launch SMA, TPD1E1B04DPYR ESD, DC block, HMC8410LP2FETR.
• Front-end filter: shunt/series 5-pole ladder using the supplied computed values.
• First conversion: ADE-1+, 45 MHz crystal filter HCI CFUMT6-45.000-F75IL03AL with identical 612.6 nH series / 16.85 pF shunt L-matches on both ports.
• IF amplification: two GALI-74+ stages, each with input/output 100 pF DC blocks, RFOUT bias choke, and approximately 2.5 Ω series feed resistor.
• Second conversion: ADE-1+ driven from an externally supplied 34.3 MHz LO through a harmonic-suppressing LC low-pass.
• Power: TPS7A2033PDBVR, TPS7A2050PDBVR, TPS60403DBVR, delayed RF-rail enable, and approximately −2 V HMC8410 gate bias.

• J1 antenna RF input, SMA edge launch.
• J2 10.7 MHz IF output, SMA edge launch.
• J5 LO1 input, SMA edge launch.
• J6 LO2 input, SMA edge launch.
• J3 raw 5 V DC input, plain two-pin header.

• Externally powered from regulated VIN_5V_RAW; no battery.
• Power-up sequencing must establish VGG_NEG before enabling V5_RF.

Diagram

• Final rail currents and thermal margin must be verified from current datasheets before the power network is accepted.
• Every regulator and active-device supply requires connected local decoupling.

• Fixed board outline: 222 mm × 64 mm.
• Four layers, targeting JLCPCB JLC04161H-3313A as closely as available.
• Verify every specified non-generic part in the live library and sourcing data; do not silently substitute discontinued or unavailable parts.
• Standard passives are 0402 where electrically and practically reasonable.

• None in Phase 1; no MCU or frequency synthesizer.

• Preserve the fixed large format; do not compact the signal chain.
• Four isolated layout zones: RF/LNA/Mixer1, IF chain, LO2 filter, and power.
• Internal ground reference planes; no top-layer ground pour beneath controlled-impedance RF runs.
• Calculate 50 Ω top-layer trace width from the actual applied stackup; 0.345 mm is only a prior reference.
• Orient each edge-launch SMA correctly for its board edge and prefer 45° routing.

• Use all named active/filter MPNs unless a real sourcing or physical conflict is identified.
• Use supplied computed BPF, FL1 match, Pad1, and Pad2 values without redesign.
• LO2 low-pass topology/value selection remains an engineering task, with cutoff between 34.3 MHz and 68.6 MHz.
• Stop and surface any inconsistent pinout, unavailable part, unsafe bias condition, or ambiguous mechanical detail rather than guessing.

• VIN_5V_RAW is a sufficiently regulated external 5 V source; connector current capacity and required input tolerance remain to be verified.
• Exact SMA MPN and board-edge assignment are not specified and require sourcing/mechanical selection.
• Exact decoupling values and all regulator support values follow current manufacturer datasheets.

• Initial specification created from the supplied Phase 1 prototype brief.