PCB Design for Smart Glasses


Correct: for the PCB board outline, Flux needs a single closed outer contour. It generally won’t use an SVG icon with multiple paths/holes as the board shape directly.
For glasses, that means:
  • ✅ Use the SVG outer perimeter as the PCB outline.
  • ❌ Don’t expect the lens openings / holes inside the glasses icon to automatically become board cutouts.
  • ✅ Add lens openings separately as mechanical cutouts / routed slots if Flux supports them in your layout flow, or represent them later for fabrication.
  • ✅ Best SVG format: one flattened filled path for the outside edge, no groups, no strokes, no masks, no transforms.
So the workflow is usually:
  1. Export only the outside silhouette of the glasses frame as one closed path.
  2. Apply that as the PCB board outline.
  3. Add any internal holes/cutouts separately as mechanical features.
For now, if you want the front of a glasses frame as the PCB, make the board outline the solid glasses-front outer shape, then treat the lens openings as separate cutouts rather than part of the SVG board-shape path.
ok I've fixed the SVG but why is it still not appearing?
I’ll re-check the updated GlassesSVG asset flags and the active layout board-shape/asset rules to see what is still preventing it from showing.
The fixed SVG was re-uploaded as a thumbnail/default asset again, so it still wasn’t eligible as a PCB board shape. I’ve now changed it to isPcbBoardShape=true, but the active board outline is still rectangle — the board shape does not automatically switch just because the asset exists.
Why it still may not appear:
  • The asset exists, but the PCB outline is still set to rectangle.
  • Flux’s board-shape rule needs the actual closed SVG path data, not just the asset name.
  • If you used an “asset” layout rule, that creates/controls a visual asset reference, not necessarily the manufactured PCB outline.
What to do next:
  1. Open the SVG file in a text editor.
  2. Copy the outer path’s d="M ... Z" value.
  3. Paste that path here.
  4. I’ll apply it directly as the board outline.
Apply outline and verify
Paste SVG path
Explain SVG path
Check current asset
Run layout review

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Schematic of EchoGlass
J2
R2
Resistance
0Ω
R5
Resistance
0Ω
R3
Resistance
0Ω
C21
Capacitance
10uF
R13
Resistance
10kΩ
C11
Capacitance
0.1uF
R15
Resistance
10kΩ
C9
Capacitance
0.1uF
R14
Resistance
10kΩ
R16
Resistance
10kΩ
C10
Capacitance
10uF
C19
Capacitance
10uF
R10
Resistance
1.0Ω
R9
Resistance
1.0Ω
R7
Resistance
1.0Ω
R12
Resistance
10kΩ
R17
Resistance
0Ω
R4
Resistance
0Ω
R6
Resistance
0Ω
R1
Resistance
0Ω
C22
Capacitance
10uF
R8
Resistance
1.0Ω
C20
Capacitance
10uF
R11
Resistance
10kΩ
C12
Capacitance
10uF
U12 OUT2 - R14 P2
U3 DATA - U4 DATA
U9 VREFB - U9 ~SHDN
U9 VDD - U9 VREFA
R10 P2 - LS2 ~
R7 P2 - LS1 ~
U11 OUT2 - R12 P2
U9 VDD - U9 VREFA
R4 P2 - U10 SCK
R9 P2 - LS2 ~
U1 CLOCK - U2 CLOCK
SPI_R_SDI
SPI_L_SCK
R15 P2 - R16 P1
U9 VREFB - U9 ~SHDN
R15 P2 - R16 P1
U11 +VS - C13 P1
R6 P2 - U10 ~CS
U9 VOUTA - R11 P1
U1 VDD - C1 P1
R13 P2 - R14 P1
U5 DATA - U6 DATA
J1 3 - J2 3
U12 –IN1 - R9 P1
R11 P2 - R12 P1
J1 3 - J2 3
U9 VDD - U9 VREFA
R1 P2 - U9 SCK
R8 P2 - LS1 ~
U7 DATA - U8 DATA
U11 +VS - C13 P1
U1 DATA - U2 DATA
R3 P2 - U9 ~CS
U10 VREFB - U10 ~SHDN
R2 P2 - U9 SDI
U11 –IN1 - R7 P1
R13 P2 - R14 P1
R11 P2 - R12 P1
U1 VDD - C1 P1
U12 OUT2 - R14 P2
U9 VDD - U9 VREFA
U10 VOUTA - R13 P1
U1 VDD - C1 P1
U11 OUT2 - R12 P2
SPI_R_SCK
U10 VREFB - U10 ~SHDN
U1 VDD - C1 P1
SPI_R_CS_N
J1 3 - J2 3
SPI_L_CS_N
R5 P2 - U10 SDI
U11 +VS - C13 P1
SPI_L_SDI
J1 SHIELD__1 - J2 1
J2 SHIELD__1 - C19 P2
U9 VSS - U9 ~LDAC
R16 P2 - C17 P2
J1 SHIELD__1 - J2 1
U9 VSS - U9 ~LDAC
J2 SHIELD__1 - C19 P2
J2 SHIELD__1 - C19 P2
U9 VSS - U9 ~LDAC
J2 SHIELD__1 - C19 P2
J2 SHIELD__1 - C19 P2
U9 VSS - U9 ~LDAC

EchoGlass

EchoGlass thumbnail