PCB Layout Design Guidance
Placing decoupling capacitors around U4...
0:42
Started: Place decoupling capacitors C2, C3, C4 around U4 on the TOP layer following the datasheet recommended layout guidelines..
Worked
0:37
Thought
Here’s the progress against your plan:
Work completed
- Project description and system architecture defined
- All major ICs and active components added to the schematic (STM32G070CBT6, BMP581, AP2112K-3.3, BQ24075, USB-C, LCD FPC, LEDs, resistors, capacitors)
- Nets connected per locked Phase-2 netlist
- Schematic reviewed; passive voltage/power ratings set; VCAP and CHG pull-ups added
- Footprints assigned; generic passives set to 0603
- Board size set to 30 mm × 20 mm; bottom layer configured as solid GND plane
- Four NPTH mounting holes placed at (±13, ±8)
- Paused after placement of mounting holes for your review of board size and mounting placement
Tasks not done / cannot automate
- Stackup configuration (2-layer FR4 1.6 mm)
- Net-class assignments and design rule width/clearance settings
- Precise placement of USB-C, LCD FPC, charger, decoupling cluster, MCU and other components
- PCB routing of power, control and signal nets
- DRC/ERC cleanup
- Gerber/Drill file/BOM/PnP/pin-map generation and packaging
Success criteria
Not yet met—the schematic is complete, but PCB layout, DRC clean-up, and fabrication outputs remain to be done.
Not yet met—the schematic is complete, but PCB layout, DRC clean-up, and fabrication outputs remain to be done.
Recommended next step
Configure the PCB stackup and layout rules (net classes, trace widths, clearances), then place the remaining components and route the board. Once routed and DRC-clean, I can generate the fabrication outputs and bundle them into SMD_V2_FAB_v1.zip.
Configure the PCB stackup and layout rules (net classes, trace widths, clearances), then place the remaining components and route the board. Once routed and DRC-clean, I can generate the fabrication outputs and bundle them into SMD_V2_FAB_v1.zip.
Flux stopped
