ARM-Based DIN Rail Controller Design
Thought for 7 mins 50 sec
Below is a solid Rev A architecture pack for your Control-X controller. I’m keeping the block diagram and partitioning high-level, and the MCU pin table only locks pins I could confirm from datasheet extraction because exact pin numbers should not be guessed . The structure also follows a clean subsystem-oriented documentation style suited to first-pass design work .
1. Schematic block diagram
2. Suggested component selection Recommended core partsDiagram
Table
| Function | Suggested part | Why it fits |
|---|---|---|
| MCU | STM32H753ZITx | Datasheet extract shows Arm Cortex-M7 up to 480 MHz, 2 MB Flash, 1 MB RAM, LQFP144, 1.62 V to 3.6 V, Ethernet MAC with DMA, 4 USART + 4 UART + 1 LPUART, 6 SPI + Quad-SPI. Very good fit for Ethernet + multiple serial ports + external flash + future expansion. |
| Ethernet PHY | LAN8720AI-CP | Datasheet extract shows RMII-only, 1.6 V to 3.6 V I/O, integrated 1.2 V regulator, nRST, and support for 50 MHz RMII REF_CLK generation from a 25 MHz crystal/oscillator. |
| Isolated RS485 | ADM2587EBRWZ | Strong Rev A choice because it combines signal isolation + isolated power in one part. Datasheet extract shows half/full duplex, 500 kbps, 3.3 V or 5 V supply, integrated isoPower, ±15 kV ESD, and high CMTI. This simplifies the isolated RS485 section a lot. |
| RS232 | MAX3232ECDR | Datasheet extract shows 3.0 V to 5.5 V, 2 drivers / 2 receivers, 4 x 0.1 uF charge-pump caps, and strong ESD on RS232 pins. Standard, low-risk choice. |
| AO DAC | DAC80501ZDGSR | Datasheet extract shows 16-bit, SPI, 2.7 V to 5.5 V, buffered voltage output, and internal or external reference. Good precision headroom for both 0-10V and 4-20mA output modes. |
| 16 MB QSPI Flash | W25Q128JVSIQ | Datasheet extract shows 128 Mbit / 16 MB, SPI / Dual / Quad SPI, 2.7 V to 3.6 V, up to 133 MHz, SOIC-8. Excellent match for config, logging, staged firmware update, and offline logic state. |
| 5V buck | LMR50410Y5FQDBVRQ1 | Datasheet extract shows 4 V to 36 V input, fixed 5.0 V, 1 A, synchronous rectification, UVLO, current limit, hiccup short protection, and thermal shutdown. Good fit for a robust industrial front end. |
| 3.3V regulator | NCP176BMX330TCG | Datasheet extract shows 1.4 V to 5.5 V input, 500 mA, low dropout, and simple 1 uF in / 1 uF out ceramics. Good if your 3.3 V budget stays comfortably below 500 mA. |
- My first-choice set is:
- The only caution is the 3.3 V rail current budget. NCP176BMX330TCG is clean and simple, but for an STM32H753ZITx system with PHY, flash, DAC, LEDs, and field I/O logic, I would verify peak 3.3 V demand before locking it in.
Table
| Sheet | Contents |
|---|---|
| Power | 12-30V input connector, reverse-polarity stage, surge clamp, input filter, 5V buck, 3.3V regulator, power flags, rail monitoring, isolated RS485 power |
| MCU | STM32H753ZITx, clocks, reset, boot configuration, decoupling, VBAT/RTC support, spare GPIO breakouts |
| Ethernet | LAN8720AI-CP, RMII nets, 25 MHz clocking, PHY reset, link LEDs, RJ45/magnetics, ESD |
| RS485 | ADM2587EBRWZ, termination enable, biasing, TVS, isolated field connector |
| RS232 | MAX3232ECDR, charge-pump capacitors, TX/RX terminal connector, protection |
| Analogue Input | 0-10V / 4-20mA selectable input, divider or shunt path, clamp/protection, RC filter, ADC handoff, optional mode-sense GPIO |
| Analogue Output | DAC80501ZDGSR, reference/filtering, output amplifier/current-loop driver, jumper selection, protection |
| Digital I/O | 2x 24V DI front end, 2x low-side DO drivers, flyback handling, connector interface |
| Storage | W25Q128JVSIQ, QSPI routing, decoupling, optional write-protect/hold strategy |
| Debug and LEDs | SWD header, service UART header, heartbeat/power/fault/activity LEDs |
- Keep Power, Ethernet, RS485, and Analogue I/O on separate sheets.
- Put all mode jumpers on the AI and AO sheets, not mixed into MCU.
- Keep Storage separate from MCU so QSPI routing and boot/update behavior stay clear.
- For the MCU symbol itself, a multi-block organization such as Power / Communication / Analog / Control / Debug / GPIO banks is the cleanest approach, matching the recommended sub-symbol grouping pattern for large ICs .
Exact pin numbers should come only from the datasheet, not memory . I could confirm some functions from datasheet extraction; others are shown as recommended assignment, finalize from full alternate-function table.
Preliminary mapping
Table
| Function | Peripheral | Proposed MCU signal(s) | Exact status |
|---|---|---|---|
| Ethernet PHY | RMII | PA1 = ETH_RMII_REF_CLK | Confirmed from datasheet extract |
| Ethernet PHY | RMII | PA2 = ETH_MDIO | Confirmed from datasheet extract |
| Ethernet PHY | RMII | PB12 = ETH_RMII_TXD0 | Confirmed from datasheet extract |
| Ethernet PHY | RMII | Remaining RMII pins: MDC, CRS_DV, RXD0, RXD1, TX_EN, TXD1 | Finalize from full AF table |
| External flash | Quad-SPI | PB6 = QUADSPI_BK1_NCS | Confirmed signal, pin number not fully locked in extraction |
| External flash | Quad-SPI | PC9 = QUADSPI_BK1_IO0 | Confirmed |
| External flash | Quad-SPI | PC10 = QUADSPI_BK1_IO1 | Confirmed signal, pin number should be rechecked in full table |
| External flash | Quad-SPI | IO2 / IO3 / CLK | Finalize from full AF table |
| RS485 | USART1 | PB14 = USART1_TX | Confirmed |
| RS485 | USART1 | PB15 = USART1_RX | Confirmed |
| RS485 DE | GPIO | Spare GPIO near USART1 bank | Select during full AF closure |
| RS232 | USART2 | PA2 = USART2_TX | Confirmed but conflicts with ETH_MDIO |
| RS232 | USART2 | USART2_RX on alternate pin | Must be remapped in full AF closure |
| Service UART | USART3 | PC10 = USART3_TX | Confirmed signal |
| Service UART | USART3 | PC11 = USART3_RX | Confirmed signal, exact package pin to recheck |
| AO DAC | SPI1 | PB3 = SPI1_SCK | Confirmed signal |
| AO DAC | SPI1 | PB4 = SPI1_MISO | Confirmed signal |
| AO DAC | SPI1 | SPI1_MOSI and SPI1_NSS on alternate pins | Finalize from full AF table |
| Analogue input | ADC1 | PA0 = ADC12_INP0 | Confirmed |
| SWD | Debug | PA13 = SWDIO, PA14 = SWCLK, NRST | Standard assignment; NRST confirmed, SWD pins should be verified in package table |
| LEDs | GPIO | Prefer spare pins on ports E/G | Reserve |
| Digital inputs | GPIO | 2 spare GPIO inputs | Reserve |
| Digital outputs | GPIO | 2 spare GPIO outputs | Reserve |
| PHY reset | GPIO | 1 spare output GPIO | Reserve |
| Future expansion | Spare | 1 extra UART/SPI/I2C instance | Reserve |
- STM32H753ZITx is still a strong fit.
- But your requested combination creates at least one obvious alternate-function collision already visible in extracted data:
- PA2 can be ETH_MDIO or USART2_TX, not both.
- So the next step is a full AF closure pass on the MCU before drawing detailed wiring.
- Use the integrated-isolation approach with ADM2587EBRWZ unless cost or availability forces a split transceiver + isolated supply.
- Put the AI and AO mode jumpers at the field-connector edge for serviceability.
- Keep RJ45 physically separated from the analog section.
- Keep AGND local to AI/AO conditioning and join to DGND intentionally at one controlled point.
- Budget board area for terminal blocks first; DIN-rail I/O density usually drives the outline more than the logic section.
The biggest architectural unknown is AO output stage choice:
- The DAC80501ZDGSR gives you an excellent control source,
- but you still need to choose whether the 0-10V and 4-20mA output stage is:
- op-amp + transistor loop driver
- integrated V/I output driver
- dual-path jumper-selectable stage
Since you said robustness over cost, I’d treat that as a dedicated design block, not an afterthought.
If you want to continue this in a new editable project
Because you’re viewing a project you can’t edit, here’s a ready-to-start project link:
If you want, I can next generate either:
- a full signal-by-signal RMII/QSPI/UART pin-closure table, or
- a Power sheet design proposal with protection and rail budgeting.
Generate pin-closure table
Power sheet proposal
AO stage recommendation
Check 3.3V budget
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