Project Idea Starter

flux

U2 — TPS63900DSKR buck-boost converter U2 pin connections

Table

U2 pinConnected netConnected components
1 — ENBAT_FUSEDF2 P2, VIN, C15 P1, C17 P1, TP_BAT
2 — SELBAT-Grounded to select the CFG3-programmed output
3 — CFG1U2_CFG1R14 P1
4 — CFG2U2_CFG2R15 P1
5 — CFG3U2_CFG3R13 P1
6 — VOUT3V3_SYSC16 P1 and downstream 3.3 V loads
7 — LX2U2_LX2L2 P2
8 — GNDBAT-Battery return
9 — LX1U2_LX1L2 P1
10 — VINBAT_FUSEDF2 P2, EN, C15 P1, C17 P1, TP_BAT
11 — EPBAT-Exposed thermal/ground pad
VIN source
J2 pin 1 / BAT+ → F2 (1 A resettable fuse) → BAT_FUSED → U2 VIN
The return is BAT-, connected to system GND through the existing R11 0 Ω star link.
Inductor
  • L2: 2.2 µH, 1.5 A rated, 2 A saturation
    • P1 → U2_LX1 → U2 pin 9
    • P2 → U2_LX2 → U2 pin 7
Capacitors
  • C15: 10 µF, 10 V X7R input bulk
    • P1 → BAT_FUSED
    • P2 → BAT-
  • C17: 100 nF, 10 V X7R input bypass
    • P1 → BAT_FUSED
    • P2 → BAT-
  • C16: 22 µF, 10 V X7R output bulk
    • P1 → 3V3_SYS
    • P2 → BAT-
Configuration resistors
  • R13: 16.2 kΩ, 1%
    • U2_CFG3 → BAT-
    • Programs the selected 3.3 V output with SEL low
  • R14: 36.5 kΩ, 1%
    • U2_CFG1 → BAT-
  • R15: 0 Ω, 1%
    • U2_CFG2 → BAT-
    • Selects the configured input-current setting
VOUT net: 3V3_SYS, nominally 3.3 V.
Review regulator wiring
Check power budget
Audit radar supply
Run full ERC
Sign up to send

Files

Schematic

Layout

3D View

Project Specification
Project Overview
  • Device: TANK_SENSOR_V1 solar-powered LiFePO4 water-level transmitter.
  • Current status: Review.
  • Current scope: Solar input protection and BQ24650 charging section completed; sensing/transmitter sections are outside this task.
Intended Use
Outdoor water-level transmitter powered by a single-cell LiFePO4 battery and replenished from a small solar panel.
What the Device Should Do
  • Accept a two-wire solar input.
  • Protect against input overcurrent, reverse polarity, and transients.
  • Hold the protected panel input near a programmed maximum-power voltage.
  • Charge one LiFePO4 cell to 3.60 V at approximately 500 mA.
  • Qualify battery temperature with an attached 10 kΩ NTC.
  • Expose charge-in-progress and charge-complete status signals.
Main Features
  • TI BQ24650RVAR synchronous solar charger.
  • 750 mA resettable fuse and series SS34.
  • Provisional input TVS.
  • External synchronous MOSFET power stage.
  • Named power, battery, sensing, and status nets.
System Architecture
Solar panel → J1 → F1 → D1 → PROTECTED_SOLAR → synchronous buck charger → BAT+ / LiFePO4 cell
Hardware Subsystems
Solar Input and Protection
  • J1 pin 1 SOLAR+; pin 2 GND.
  • F1 750 mA PTC, D1 SS34, D2 provisional SMBJ18A TVS.
  • C1 10 µF / 35 V and C2 100 nF / 50 V ceramic input capacitors.
Charger and Power Stage
  • U3 BQ24650RVAR, RVA 16-pin VQFN with exposed pad.
  • Q1/Q2 Si7288DP dual N-channel MOSFET packages, each package halves paralleled for high-side and low-side service.
  • L1 22 µH and C11 6.8 µF nominal produce about 13.0 kHz LC resonance.
  • R12 80 mΩ Kelvin shunt sets approximately 500 mA.
  • Bootstrap, REGN/VREF/VCC decoupling, sense filters, and gate damping are populated.
  • The IC has internal compensation and digital soft-start; no external COMP or SS pin exists.
Programming and Temperature
  • MPPSET: 316 kΩ upper / 100 kΩ lower, approximately 4.992 V at the protected input.
  • VFB: 71.5 kΩ upper / 100 kΩ lower, approximately 3.6015 V.
  • TS: 5.23 kΩ from VREF to TS, 30.1 kΩ and 103AT-2 NTC from TS to GND.
  • TERM_EN tied to VREF to enable normal charge termination.
Status and Battery Interfaces
  • CHARGE_STATUS = STAT1, open-drain with 10 kΩ pull-up to VREF; LOW means charging.
  • CHARGE_DONE = STAT2, open-drain with 10 kΩ pull-up to VREF; LOW means charge complete.
  • J2 exposes BAT+ and BAT-.
  • R11 is the explicit 0 Ω star connection from BAT- to system GND.
Interfaces and Connections
  • J1: SOLAR+, GND.
  • J2: BAT+, BAT-.
  • J3: VREF, CHARGE_STATUS, CHARGE_DONE, GND.
Power and Runtime Expectations
  • Charge target: 3.60 V, 500 mA maximum programmed current.
  • Downstream transmitter power budget and battery capacity/runtime are not yet defined.
Power Tree and Power Budget

Table

PathProgrammed/Allowed CurrentNotes
Solar input protection750 mA PTC holdThermal derating must be checked
Charger output500 mA40 mV / 80 mΩ
Battery1S LiFePO43.60 V regulation
Manufacturing and Assembly Expectations
  • SMD charger and power stage; screw terminals for panel and battery.
  • Verify all REVIEW footprints and select a production inductor MPN before layout.
Physical Design Expectations
  • Keep input capacitors, MOSFET switching loop, bootstrap parts, REGN capacitor, inductor, and shunt loop compact.
  • Kelvin-route SRP/SRN directly to opposite sides of R12.
  • Keep VFB, MPPSET, and TS away from PH and gate-drive copper.
Important Design Decisions
  • Retain user-required 750 mA PTC and SS34 despite headroom loss.
  • Program MPPT from the protected input, not connector-side SOLAR+.
  • Use a deliberate BAT- to GND star link rather than silently merging returns.
  • Use the TI-recommended 103AT-2 temperature network and enabled termination.
Assumptions and REVIEW Items
  • Solar panel Voc is unknown. D2 SMBJ18A is provisional; verify its 18 V standoff against panel Voc and surge requirements.
  • The 4.992 V protected-input MPP target is essentially at the BQ24650 5 V recommended VCC minimum. Series PTC/SS34 losses mean panel-side MPP must be roughly 5.35–5.50 V at 500 mA.
  • Verify PTC hold-current derating at maximum enclosure temperature.
  • Verify the Flux Si7288DP footprint against the official PowerPAK SO-8 land pattern.
  • Select and verify an exact 22 µH shielded inductor MPN/footprint with Isat ≥2 A and Irms ≥1.5 A.
  • Confirm effective C11 capacitance under DC bias remains near the stability target.
Change Notes
  • Created the complete solar charging schematic section and set project metadata.
  • ERC and selected schematic/passive checks are clean at the end of this pass.

  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Solar Input and Protection

  • Charger and Power Stage

  • Programming and Temperature

  • Status and Battery Interfaces

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions and REVIEW Items

  • Change Notes