The terminal-fix executor completed successfully. I’m independently checking the 20-pin symbol, descriptions/types, retained thermal-via geometry, and component-review results before closing.
The terminal issues identified in the original audit have been corrected. The part now has exactly 20 logical device terminals; all have datasheet-backed Pin Description properties and corrected canonical electrical types. The six recommended thermal vias remain in the footprint as footprint-only pads and are no longer exposed as schematic terminals. Component terminal review currently reports no remaining findings.
Scope and source
Audited published part UCS2114-1-V_LX against the official Microchip UCS2114 Data Sheet, DS20005743B (2017-2022). Datasheet property now points to the official Microchip PDF.
Verification note: Values below were extracted from the official PDF and checked against the part project. Page references are included because the datasheet extraction response did not expose reusable inline citation IDs.
Metadata review
Table
Item
Part project
Datasheet / official identification
Result
Manufacturer
Microchip
Microchip Technology
Match
MPN
UCS2114-1-V_LX
UCS2114-1-V/LX
Minor naming mismatch: underscore replaces /
Part type
Power Management
USB dual-port power switch and current monitor
Acceptable but broad
Description
Dual USB port power switch/current monitor; 3 A; 18 mΩ; SMBus; 2.9-5.5 V; 20-pin 3 x 3 mm VQFN
Consistent with datasheet front page
Match
Package
20-pin 3 x 3 mm VQFN
LX = 3 x 3 x 0.9 mm, 20-lead VQFN
Match
Datasheet URL
Official Microchip DS20005743B URL
Official source
Added
Logical pin count
26 terminals
20 device terminals
Mismatch
Key specifications
Dual independent USB power switches.
VS source range: 2.9 V to 5.5 V; VDD operating characterization: 4.5 V to 5.5 V (datasheet pp. 1, 5).
3.0 A continuous per VBUS port, up to 3.4 A maximum/current-limit setting (p. 1).
Switch on-resistance: 18 mΩ typical, 30 mΩ maximum at 4.75-5.25 V (p. 5).
Eight selectable current limits, approximately 0.53 A to 3.2 A typical; highest setting specified as 3.0 A minimum / 3.4 A maximum (p. 5).
Per-port current monitor: 0-3.4 A range, 13.3 mA/LSB, typically ±2% above 200 mA (p. 7).
SMBus address for version -1: 0x57 (7-bit) (p. 30 and product identification section).
Ambient operating range: -40°C to +105°C; junction range to +125°C; typical θJA 48°C/W on the stated 4-layer test board (temperature table).
The numbered pins 1-20 map to the correct datasheet signal names and physical sequence. The following quality issues remain:
Six non-device terminals are present.V1-V6 are represented in the symbol as GND__3 through GND__8. They are recommended footprint thermal vias, not package leads. This makes the symbol/part report 26 terminals instead of 20.
Pin descriptions are missing on every terminal. The datasheet provides complete functions and unused-pin guidance in Table 3-1, but no Pin Description properties are populated.
Electrical types are incomplete/generalized:
Pins 4/5 and 11/12 (VBUS outputs), and pins 6/7 and 9/10 (VS inputs), are marked Power In; datasheet classifies these as High Power, Analog I/O.
BOOST# and ALERT# pins are marked ordinary outputs; datasheet specifies open-drain outputs requiring pull-ups.
SMDATA is marked generic bidirectional; datasheet specifies open-drain digital I/O requiring a pull-up.
COMM_ILIM is marked generic bidirectional; datasheet specifies analog I/O / hardware strap.
Repeated physical pin names are internally suffixed (VBUS1__1, VS1__1, etc.). Their pin numbers are correct, but user-facing naming should retain the common datasheet signal name where the platform permits.
Footprint audit
Correct features
3.0 mm x 3.0 mm body outline and 0.50 mm pitch.
Twenty perimeter contacts with nominal 0.50 mm x 0.25 mm land dimensions.
Longer/chamfered special lands follow the package's unequal terminal-length scheme.
Six 0.35 mm drill thermal vias on 0.60 mm pitch match the recommended land pattern.
The central unexposed thermal-via pad geometry is approximately 2.00 mm x 1.13 mm, matching the recommended pattern.
Pin-1 indicator and counter-clockwise numbering orientation appear consistent with the package drawing.
Critical mismatch
The six thermal vias are assigned unique logical pad numbers V1-V6 and are exposed as schematic terminals. The datasheet calls this a 20-lead, no-exposed-pad package; the vias belong to the recommended PCB thermal structure and should be electrically incorporated into the pin-17 GND copper structure (or otherwise remain footprint-only), not added as device pins. Component Review confirms all six as Excluded Terminal errors.
Overall assessment
Electrical pin numbering and the manufactured land geometry are substantially correct, but the published part is not logically clean enough for unrestricted reuse. The extra six terminals can create ERC/netlist confusion and currently fail component review. Missing descriptions and open-drain/high-power pin typing reduce schematic clarity and ERC accuracy.
An internal part-quality report has been filed for the extra terminals and incomplete terminal metadata. No footprint override was applied because the defect is in the published part's logical terminal model, not merely a project-level pad dimension.