All have correct source dimensions but compute at 0.001× scale, so none are manufacturing-safe. This appears to affect imported KiCad PDIP footprints generally, not only TC4420CPA.
Flux support documentation does not list a specific workaround for the KiCad 0.001× footprint scaling defect.
The only documented fallback is to:
Ensure the .kicad_mod uses a supported KiCad format.
Remove the imported footprint asset.
Rebuild the footprint with native Flux pads using explicit millimeter dimensions.
A Scale rule is documented for SVG/3D assets, but not as a reliable correction for imported KiCad pad geometry. Since this is a reproducible platform bug, report the project and reproduction details through Contact Support.
Reviewed available part information for the published Flux part TC4420CPA, including MPN, manufacturer, package, pin count, description, project properties, schematic terminals, and PCB footprint geometry. Cross-checked against the official Microchip TC4420/TC4429 datasheet.
Datasheet
Existing Datasheet URL before review: http://uk.rs-online.com/web/p/products/6811124P
Datasheet note: duplicate VDD, GND, and OUTPUT pins must both be connected for proper operation.
Symbol and Terminal Metadata Findings
Pin numbering and terminal names match the official 8-pin PDIP/SOIC/CERDIP pinout.
Pin descriptions are not populated on the Flux terminals.
Pin Type is Unspecified on all terminals; recommended types are: VDD = Power In, GND = Ground, INPUT = Input, OUTPUT = Output, NC = Not Connected.
Grouping/sections are not populated; useful groups would be Power, Ground, Logic Input, Driver Output, and No Connect.
Footprint Cross-Check
The PCB footprint appears to use the correct 8-pin DIP topology:
4 pins per side.
2.54 mm pitch along each row.
Approximately 7.94 mm row spacing, consistent with an 8-lead 300 mil PDIP land pattern region.
Pin 1 is indicated by a rectangular pad and silkscreen chamfer/notch treatment.
However, the computed pad size is approximately 0.00116 mm x 0.00116 mm, and pads do not visibly render in the flat footprint view. This is not manufacturable for an 8-PDIP through-hole part. A practical PDIP footprint should have plated through-holes and annular pads sized for the lead dimensions and fabrication capabilities, commonly around a 0.8-1.0 mm drill with around 1.5-1.8 mm pad diameter depending on fab rules.
Mismatches / Issues Flagged
Datasheet URL was not the official datasheet PDF; updated to the official Microchip PDF.
Pin names and pin numbers match the datasheet.
Pin descriptions are missing.
Pin electrical types are all Unspecified instead of functional types.
Footprint pad placement/topology is broadly correct for PDIP-8, but pad sizes are effectively zero and therefore not manufacturable.
A part quality issue was filed for the footprint pad-size problem.
Recommended Follow-Up Fixes
Populate Pin Description and Pin Type properties for all terminals.
Repair the PDIP-8 footprint pad geometry with proper plated through-hole drill and annular pad sizes.
Re-run part review checks after metadata and footprint repair.