Part Review Report

flux

The part already has an ST datasheet URL set, so I’m using that as the reference and moving straight into pin/package verification.

flux

The pin-number/name mapping matches the ST UFQFPN48 pinout overall; I’m documenting the metadata and footprint issues I found so the detailed comparison stays in the project files.
Created a project doc

Part Review Report: STM32WL55CCU6

View Document
Date: 2026-07-13 Official datasheet already set on the part: https://www.st.com/resource/en/datasheet/stm32wl55cc.pdf

flux

Review complete. The datasheet URL was already set to the official ST datasheet, so no Datasheet property update was needed; I created the detailed findings in Part Review Report: STM32WL55CCU6.
Key results: the 49-pin symbol/pin-number mapping matches the ST UFQFPN48 pinout, but metadata has issues: package is incorrectly set to TO, all pin types are Unspecified, pin descriptions are missing, logic metadata appears wrong, and the footprint looks like a generic QFN pattern rather than the exact ST recommended UFQFPN48 land pattern. Suggested next step: ask me to apply the metadata/pin-description/footprint corrections.
Fix metadata and footprint
Update part metadata
Populate pin descriptions
Correct footprint geometry
Run part checks

Refine this doc
Ask about this doc
Part Review Report: STM32WL55CCU6
Date: 2026-07-13
Reference sources
  • Official datasheet already set on the part: https://www.st.com/resource/en/datasheet/stm32wl55cc.pdf
  • ST product page/web confirmation: STM32WL55CCU6 is active/in volume production and uses UFQFPN48 7 x 7 x 0.55 mm.
  • Datasheet source: STMicroelectronics DS13293 Rev 5, December 2022.
Current part metadata found in Flux

Table

FieldCurrent valueDatasheet / official expected valueStatus
Manufacturer Part NumberSTM32WL55CCU6STM32WL55CCU6OK
ManufacturerSTMicroelectronicsSTMicroelectronicsOK
DescriptionMultiprotocol LPWAN dual core 32-bit Arm Cortex-M4/M0+ LoRa, (G)FSK, (G)MSK, BPSK, up to 256KB flash, 64KB SRAMMatches datasheet summaryOK
Datasheet URLhttps://www.st.com/resource/en/datasheet/stm32wl55cc.pdfOfficial ST datasheet URLOK; no update needed
Terminal count / pads4948 leads plus exposed pad pin 49OK
Part TypeIntegrated CircuitsMicrocontroller / RF SoC, or singular Integrated Circuit in Flux optionsMismatch / suboptimal
Package or Case CodeTOUFQFPN48, 7 x 7 x 0.55 mm, 0.5 mm pitchMismatch
Type-specific values from library searchIC Type: Logic; Logic Function: ANDWireless MCU / RF transceiver SoCMismatch
Key datasheet specs
  • Device family: STM32WL55xx multiprotocol LPWAN wireless microcontroller / RF SoC.
  • Cores: dual-core Arm Cortex-M4 / Cortex-M0+.
  • Memory for STM32WL55CC: 256 KB flash, 64 KB SRAM.
  • Radio: 150 MHz to 960 MHz; LoRa, (G)FSK, (G)MSK, BPSK.
  • RF output power: high-power PA programmable up to +22 dBm; low-power PA programmable up to +15 dBm.
  • Supply: 1.8 V to 3.6 V main operating voltage.
  • Temperature suffix 6: -40 °C to +85 °C ambient at maximum power dissipation; junction limit up to 105 °C.
  • Ordering decode for STM32WL55CCU6: C = 48-pin count, C = 256 KB flash, U = UFQFPN, 6 = -40 °C to +85 °C.
  • Absolute maximum main supply: -0.3 V to 3.9 V for VDD/VDDA/VDDRF/VDDSMPS/VBAT/VREF+ domains.
Schematic symbol pin cross-check
The schematic contains 49 terminal symbols and all listed pin numbers map to the ST UFQFPN48 pinout. Pin 49 is present as the exposed pad.

Table

PinDatasheet pin nameCurrent schematic terminalStatus
1PB3PB3OK
2PB4PB4OK
3PB5PB5OK
4PB6PB6OK
5PB7PB7OK
6PB8PB8OK
7PA0PA0OK
8PA1PA1OK
9PA2PA2OK
10PA3PA3OK
11VDDVDD_1Alias used for duplicate VDD pin
12PA4PA4OK
13PA5PA5OK
14PA6PA6OK
15PA7PA7OK
16PA8PA8OK
17PA9PA9OK
18NRSTNRSTOK
19PH3-BOOT0PH3-BOOT0OK
20RFI_PRFI_POK
21RFI_NRFI_NOK
22RFO_LPRFO_LPOK
23RFO_HPRFO_HPOK
24VR_PAVR_PAOK
25VDDPAVDDPAOK
26OSC_INOSC_INOK
27OSC_OUTOSC_OUTOK
28VDDRFVDDRFOK
29VDDRF1V55VDDRF1V55OK
30PB0-VDD_TCXOPB0-VDD_TCXOOK
31PB2PB2OK
32PB12PB12OK
33PA10PA10OK
34PA11PA11OK
35PA12PA12OK
36PA13PA13OK
37VBATVBATOK
38PC13PC13OK
39PC14-OSC32_INPC14-OSC32_INOK
40PC15-OSC32_OUTPC15-OSC32_OUTOK
41VDDAVDDAOK
42PA14PA14OK
43PA15PA15OK
44VDDVDD_2Alias used for duplicate VDD pin
45VFBSMPSVFBSMPSOK
46VDDSMPSVDDSMPSOK
47VLXSMPSVLXSMPSOK
48VSSSMPSVSSSMPSOK
49VSS exposed padGNDFunctional alias, but name differs from datasheet
Pin descriptions and electrical type metadata
Current terminal metadata is incomplete: every terminal has Pin Type: Unspecified, and no Pin Description entries are populated. The datasheet provides pin types, so the part should ideally be enriched as follows:
  • GPIO pins: I/O / bidirectional or programmable, with descriptions including major alternate functions.
  • RF input pins: RFI_P and RFI_N as Input.
  • RF output pins: RFO_LP and RFO_HP as Output.
  • Clock pins: OSC_IN as Input and OSC_OUT as Output; PC14/PC15 also support 32 kHz oscillator functions.
  • Power/supply pins: VDD, VBAT, VDDA, VDDRF, VDDRF1V55, VDDPA, VR_PA, VFBSMPS, VDDSMPS, VLXSMPS, VSSSMPS as supply/power pins as appropriate.
  • Exposed pad pin 49 should be VSS/Ground and must be connected to PCB ground.
Footprint cross-check
Current footprint asset: QFN50P700X700X65-49N-D.kicad_mod.
Datasheet package and land-pattern requirements:
  • Package: UFQFPN48, 48 leads, 7 x 7 mm body, 0.5 mm pitch, exposed die pad.
  • Recommended footprint figure: overall reference 7.30 mm x 7.30 mm, peripheral land width 0.30 mm, peripheral land length 0.55 mm, exposed pad land 5.60 mm x 5.60 mm.
  • Datasheet note: exposed pad pin 49 must be connected to VSS / PCB ground.
Observed footprint from Flux layout inspection:
  • Lead count / pad count: 48 perimeter pads plus center exposed pad = 49 pads. OK.
  • Pitch: pad center spacing appears 0.50 mm. OK.
  • Body/silk outline: 7 x 7 mm outline visible. OK.
  • Center exposed pad: reported about 5.70 mm x 5.70 mm, while datasheet recommends 5.60 mm x 5.60 mm. Minor mismatch.
  • Perimeter pad size: reported about 0.30 mm x 0.85 mm, while datasheet recommended footprint lists 0.30 mm x 0.55 mm. Likely mismatch; the imported/generic QFN footprint appears longer than the ST recommended footprint.
  • Footprint filename identifies a generic QFN pattern (QFN50P700X700X65-49N-D), not the exact ST UFQFPN48 land-pattern drawing.
Mismatches / issues to address
  1. Package metadata is wrong: Package or Case Code = TO; should be UFQFPN48 / 48-lead QFN-family package, 7 x 7 x 0.55 mm, 0.5 mm pitch.
  2. Part classification is suboptimal: Integrated Circuits should be Microcontroller, RF Transceiver, or singular Integrated Circuit depending on library taxonomy.
  3. Type-specific logic metadata is wrong: library search shows IC Type = Logic and Logic Function = AND, which does not describe this wireless MCU/RF SoC.
  4. All pins have Pin Type = Unspecified; datasheet pin electrical types are available and should be populated.
  5. Pin descriptions are missing; the datasheet table provides enough data to add short descriptions / major alternate functions.
  6. Pin 49 is named GND in the symbol/footprint while the datasheet names it VSS exposed pad. Functionally equivalent if connected to ground, but not a literal name match.
  7. The footprint appears to be a generic QFN land pattern rather than the ST recommended UFQFPN48 pattern; peripheral land length and exposed pad size should be corrected or verified against the ST footprint drawing.
  • Update package metadata to UFQFPN48 or the closest Flux-supported package code, with dimensions documented as 7 x 7 x 0.55 mm, 0.5 mm pitch, 49 pads including exposed pad.
  • Change part type to Microcontroller if the taxonomy allows; otherwise use singular Integrated Circuit and remove incorrect logic-function metadata.
  • Populate pin type and short pin descriptions from Table 20 of the datasheet.
  • Consider renaming exposed pad terminal from GND to VSS or VSS_EP while preserving its ground function.
  • Replace or edit the footprint to match ST Figure 32 recommended footprint: 0.30 mm x 0.55 mm perimeter lands and 5.60 mm x 5.60 mm exposed pad land, unless the current generic footprint was intentionally selected for a specific assembler/process.

  • Reference sources

  • Current part metadata found in Flux

  • Key datasheet specs

  • Schematic symbol pin cross-check

  • Pin descriptions and electrical type metadata

  • Footprint cross-check

  • Mismatches / issues to address

  • Recommended corrections

Documents

Assets

STM32WL55CCU6

STM32WL55CCU6 Symbol.svgDefault
STM32WL55CCU6

STM32WL55CCU6

STM32WL55CCU6.stp3D Model
STM32WL55CCU6-thumb.png

STM32WL55CCU6-thumb.png

STM32WL55CCU6-thumbThumbnail

STM32WL55CCU6

QFN50P700X700X65-49N-D.kicad_modFootprint

STM32WL55CCU6

STM32WL55CCU6 thumbnail
IC RF TxRx + MCU 802.15.4 LoRaWAN 1.0, Sigfox 150MHz ~ 960MHz 48-UFQFN Exposed Pad
Wireless microcontroller with integrated LoRa®/FSK radio, featuring a dual-core Arm® Cortex®-M4 (up to 48 MHz) and Cortex®-M0+ architecture for sub-GHz wireless applications. It includes 256 KB Flash, 64 KB SRAM, an integrated 150 MHz to 960 MHz radio, and supports SPI, I²C, USART, USB 2.0, ADC, DAC, and low-power timers, operating from 1.8 V to 3.6 V in a 48-pin UFQFPN package.
#WirelessMCU #STM32WL55CCU6 #LoRa #SubGHz #CortexM4 #CortexM0Plus #STMicroelectronics #LowPowerMCU #EmbeddedSystems #IoT

Properties

STM32WL55CCU6

STMicroelectronics

RF Transceiver

st.com/resource/en/datasheet/dm00697314.pdf

U

48-UFQFPN (7x7)

parametric-v1

creativecommons.org/licenses/by/4.0/

Pricing & Availability

DPN

Stock

Qty 1

3

0–9.2K

$4.342–$5.131

1

1.4K

$9.82

3

258–9.2K

$4.342–$10.115

Controls