STM32G051K8T6 Audit

C

cherepanyadima

Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.

flux

I’ll apply this to the current STM32G051K8T6 part: classify pins into datasheet-backed sections, remove Pin Group, assign balanced left/right orientations and terminal order, while preserving every pin number and mapping.
Created a project doc

STM32G051K8T6 Part Audit

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Manufacturer: STMicroelectronics Official datasheet: https://www.st.com/resource/en/datasheet/stm32g051f8.pdf

flux

Updated the STM32G051K8T6 symbol directly: all 32 pins retain their original numbering and mapping, with datasheet-backed sections, balanced orientations, unique terminal order, and no Pin Group properties. The official ST datasheet URL and pin descriptions/types were also added; the full findings are in STM32G051K8T6 Part Audit.
  • No pinout or mapping mismatches found.
  • Footprint matches LQFP32; pads are slightly larger than ST’s example land pattern, but remain a plausible alternate geometry.
Review, fix footprint
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Use ST land pattern
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Files

Pins

Symbol

Layout

Preview

PA2
Pin Number
9
VSS/VSSA
Pin Number
5
PA0
Pin Number
7
PB1
Pin Number
16
PB6
Pin Number
30
PA5
Pin Number
12
PA3
Pin Number
10
PB9
Pin Number
1
PA1
Pin Number
8
VDD/VDDA
Pin Number
4
PA11_PA9
Pin Number
22
PB2
Pin Number
17
PB3
Pin Number
27
PB4
Pin Number
28
PC15-OSC32_OUT
Pin Number
3
PA15
Pin Number
26
PA13
Pin Number
24
PA7
Pin Number
14
PA6
Pin Number
13
PB5
Pin Number
29
PC6
Pin Number
20
PF2-NRST
Pin Number
6
PC14-OSC32_IN
Pin Number
2
PA10
Pin Number
21
PB8
Pin Number
32
PA14-BOOT0
Pin Number
25
PB0
Pin Number
15
PA9
Pin Number
19
PA8
Pin Number
18
PA12_PA10
Pin Number
23
PA4
Pin Number
11
PB7
Pin Number
31
STM32G051K8T6 Part Audit
Source
Current part metadata
  • MPN: STM32G051K8T6
  • Manufacturer: STMicroelectronics
  • Description: Arm Cortex-M0+ STM32G0 MCU, 32-bit, 64 MHz, 64 KB Flash, 32-LQFP
  • Package: LQFP32, 7 x 7 mm body, 0.80 mm pitch
  • Pin/pad count: 32
  • Designator prefix: U
  • Datasheet URL: official ST PDF stored in the part properties
Key specifications
  • CPU: Arm Cortex-M0+
  • Maximum system clock: 64 MHz
  • Flash: 64 KB
  • SRAM: 18 KB total; 16 KB with hardware parity support
  • Supply range: 1.7 V to 3.6 V
  • Temperature grade suffix 6: -40 °C to +85 °C ambient
  • Package: 32-pin LQFP, nominal 7 x 7 mm body and 9 x 9 mm lead span
  • Interfaces/features include USART, SPI/I2S, I2C, timers, 12-bit ADC, and DAC resources as defined by the device variant
Symbol and pin audit
  • All physical pins 1 through 32 occur exactly once.
  • Every pin number and terminal mapping matches the STM32G051KxT LQFP32 datasheet pinout.
  • No pins were renamed, renumbered, replaced, or remapped.
  • PA11_PA9 and PA12_PA10 are Flux-safe forms of the datasheet labels PA11 [PA9] and PA12 [PA10]; mappings are correct.
  • Pin electrical types and concise datasheet-backed descriptions are populated for all terminals.
Symbol organization applied
Sections are ordered:
  1. Power
  2. Clock / Reset / Boot
  3. GPIO Port A
  4. GPIO Port B / Other
  5. Ground
All 32 terminals have a Section, Pin Orientation, and unique Terminal Order. Pin Group was removed from every terminal as requested. Left/right distribution is balanced per section:
  • Power: 1 left
  • Clock / Reset / Boot: 2 left / 2 right
  • GPIO Port A: 8 left / 7 right
  • GPIO Port B / Other: 6 left / 5 right
  • Ground: 1 right
Footprint audit
  • Pad count and counter-clockwise numbering from pin 1 are correct.
  • Nominal pitch and package outline correspond to LQFP32: 0.80 mm pitch, approximately 7 x 7 mm body, 9 x 9 mm lead span.
  • Existing pad size: approximately 0.508 x 1.3589 mm.
  • ST example land size is approximately 0.45 x 1.2 mm with approximately 9.8 x 9.8 mm overall soldering area.
  • Existing pads are approximately 0.058 mm wider and 0.159 mm longer than the ST example. This is a minor plausible alternate land pattern, not an unambiguous defect; no footprint geometry was changed.
  • Pin-1 marking is present and associated with pad 1.
Mismatches and risk flags
  • No critical pinout or mapping mismatches found.
  • Resolved metadata gap: the official ST datasheet URL was missing and has been added.
  • Resolved symbol metadata gap: terminal Pin Type and Pin Description were previously missing/unspecified and are now populated.
  • Minor footprint deviation: pads are slightly larger than ST's example land pattern. Confirm against the intended assembly process and preferred IPC density level if strict land-pattern conformity is required.
Final status
The part is internally consistent and usable. The only remaining review item is whether the slightly enlarged pad geometry is preferred for the target fabrication/assembly process.

  • Source

  • Current part metadata

  • Key specifications

  • Symbol and pin audit

  • Symbol organization applied

  • Footprint audit

  • Mismatches and risk flags

  • Final status