Part Datasheet Audit
Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.
Thought for 12 sec
I’ll audit the part metadata, source the official TI datasheet if needed, then verify the symbol, footprint, and pin descriptions and document any mismatches.
Worked for 6 mins 29 sec
Created a project doc
SN74LVC32AQPWRQ1 Part Datasheet Audit
Reviewed the part/project metadata, all 14 terminals, rendered schematic symbol, PCB footprint source, and TI's official SN74LVC32A-Q1 Rev. ...
Audit complete. The pin mapping and TSSOP-14 footprint broadly match TI’s datasheet; key issues are missing Part Type/Package metadata, unspecified pin electrical types, absent pin descriptions/groups, and minor footprint land-pattern differences. The existing Datasheet URL already contains the correct TI datasheet, so it was not changed.
Full findings: SN74LVC32AQPWRQ1 Part Datasheet Audit.
Fix metadata and verify
Fix pin metadata
Set package fields
Improve symbol structure
Check footprint risk
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SN74LVC32AQPWRQ1 Part Datasheet Audit
Audit scope
Reviewed the part/project metadata, all 14 terminals, rendered schematic symbol, PCB footprint source, and TI's official SN74LVC32A-Q1 Rev. E datasheet (SCAS706E, revised December 2024).
Source documents
- Existing Datasheet URL:
https://storage.googleapis.com/graviton-electric-symbols/document_assets/user-uploaded/677f11d304f58b3c8997a6e17b25525a9d298ef173c7e669d863033685edf08f.pdf - Official TI datasheet:
https://www.ti.com/lit/ds/symlink/sn74lvc32a-q1.pdf - TI orderable-part page:
https://www.ti.com/product/SN74LVC32A-Q1/part-details/SN74LVC32AQPWRQ1
The existing Datasheet URL is populated and resolves to the correct official datasheet content, so no property update was required.
Existing part information
Table
| Field | Existing value | Assessment |
|---|---|---|
| MPN | SN74LVC32AQPWRQ1 | Correct |
| Manufacturer | Texas Instruments | Correct |
| Description | Automotive Catalog Quadruple 2-Input Positive-OR Gate | Functionally correct; TI wording is “Automotive Quadruple 2-Input Positive-OR Gate” |
| Pin count | 14 | Correct |
| Package property | Not set | Missing |
| Part Type | Not set | Missing |
| Datasheet URL | Populated | Correct datasheet content; URL is an uploaded mirror rather than the canonical TI URL |
| Designator prefix | IC | Acceptable |
Key datasheet specifications
- Function: four independent 2-input positive-OR gates,
Y = A + B. - Automotive qualified.
- Orderable package: PW, 14-pin TSSOP, TI outline PW0014A, JEDEC MO-153.
- Operating supply: 2.0 V to 3.6 V; description also specifies normal 2.7 V to 3.6 V operation.
- Inputs tolerate 0 V to 5.5 V.
- Output drive: ±24 mA at VCC = 3.0 V; ±12 mA at VCC = 2.7 V.
- Propagation delay: maximum 3.8 ns at VCC = 3.3 V ± 0.3 V, CL = 50 pF.
- Operating temperature: −40 °C to +125 °C.
- Absolute maximum VCC: −0.5 V to 6.5 V.
- ESD: HBM ±2 kV; CDM ±1 kV.
- Static supply current: maximum 10 µA at VCC = 3.6 V with inputs at rails and outputs unloaded.
Pin cross-check
Table
| Pin | Part terminal | Datasheet function | Result |
|---|---|---|---|
| 1 | 1A | Channel 1 input A | Correct mapping; type/description missing |
| 2 | 1B | Channel 1 input B | Correct mapping; type/description missing |
| 3 | 1Y | Channel 1 output Y | Correct mapping; type/description missing |
| 4 | 2A | Channel 2 input A | Correct mapping; type/description missing |
| 5 | 2B | Channel 2 input B | Correct mapping; type/description missing |
| 6 | 2Y | Channel 2 output Y | Correct mapping; type/description missing |
| 7 | GND | Ground | Correct mapping; type/description missing |
| 8 | 3Y | Channel 3 output Y | Correct mapping; type/description missing |
| 9 | 3A | Channel 3 input A | Correct mapping; type/description missing |
| 10 | 3B | Channel 3 input B | Correct mapping; type/description missing |
| 11 | 4Y | Channel 4 output Y | Correct mapping; type/description missing |
| 12 | 4A | Channel 4 input A | Correct mapping; type/description missing |
| 13 | 4B | Channel 4 input B | Correct mapping; type/description missing |
| 14 | VCC | Positive supply | Correct mapping; type/description missing |
All terminal pin numbers and names match the TI top-view pinout exactly. However, every terminal currently has
Pin Type = Unspecified; descriptions, groups, sections, and terminal orders are unset. Expected electrical types are Input for A/B pins, Output for Y pins, Ground for pin 7, and Power In for pin 14.Schematic symbol review
- All 14 pins are present and mapped correctly.
- Pin-number sequence is correct.
- The symbol is a single generic rectangular package-style block, rather than four separate OR-gate units plus power. This is electrically valid but less useful and less conventional for logic schematic readability.
- Pins 1–7 are placed on the left and pins 8–14 on the right, following package sequence rather than functional signal flow.
Footprint cross-check
Existing footprint asset:
SOP65P640X120-14N.kicad_mod.Table
| Item | Existing footprint | TI PW0014A | Assessment |
|---|---|---|---|
| Pad count | 14 | 14 | Correct |
| Pad numbering | 1–14 | 1–14 | Correct |
| Pitch | 0.65 mm | 0.65 mm | Correct |
| Pad width | 0.45 mm | 0.45 mm recommended | Correct |
| Pad length | 1.475 mm | 1.50 mm recommended | 0.025 mm shorter; minor deviation |
| Row center spacing | 5.876 mm | 5.8 mm recommended land-pattern span parameter | Close but not identical; verify source convention before release |
| Body drawing | 5.0 mm × 4.4 mm | nominal 5.0 mm × 4.4 mm | Correct |
| Maximum height | Encoded as 1.2 mm | 1.2 mm max | Correct |
Pad-to-terminal mapping is correct for all pins. No missing, duplicated, or swapped pads were found.
The footprint's internal structured/computed representation reports some dimensions at a 1000× scale mismatch compared with the attached KiCad source, and computed package size is zero. The KiCad source itself contains plausible millimetre geometry and was used for this audit. This should be treated as a Flux representation/import-quality warning rather than evidence that the copper source is 1000× undersized.
Mismatches and risks
Significant metadata issues
- Part Type is missing.
- Package is missing; it should identify PW / TSSOP-14 / PW0014A.
- All terminal electrical types are Unspecified, reducing ERC effectiveness.
- Every pin description is missing.
- Pin Group, Section, and Terminal Order are missing.
Footprint cautions
- Pad length is 1.475 mm versus TI's 1.50 mm example land pattern, a minor 0.025 mm difference.
- Row spacing differs slightly from the TI example land-pattern value; the footprint may follow a different IPC nominal convention, but it should be intentionally confirmed.
- Computed footprint units/package-size metadata appear internally inconsistent despite correct-looking source geometry.
- Imported text stroke metadata appears anomalous and should be visually checked in fabrication/silkscreen views.
Symbol quality issue
The single rectangular symbol is not functionally wrong, but a multi-unit four-gate symbol would communicate the device function more clearly and allow each OR gate to be placed independently.
Overall assessment
The MPN, manufacturer, description, pin count, pin-number/name mapping, nominal package family, body size, and fundamental footprint pad arrangement agree with the TI datasheet. The largest deficiencies are incomplete metadata and terminal semantics, not an incorrect pinout. The footprint is broadly consistent with TI PW0014A, with small land-pattern differences and an internal unit-reporting anomaly that merit confirmation before publishing or manufacturing.
Audit scope
Source documents
Existing part information
Key datasheet specifications
Pin cross-check
Schematic symbol review
Footprint cross-check
Mismatches and risks
Significant metadata issues
Footprint cautions
Symbol quality issue
Overall assessment
