Part Datasheet Review and Update
Package or Case Code is wrong: currently TO, should be STQFN/TQFN-20 2 × 3 mm, 0.4 mm pitch.SLG46826V. Cross-check source was the official Renesas SLG46826 datasheet and Renesas product information.Datasheet URL property: https://www.renesas.com/us/en/products/programmable-mixed-signal-asic-ip-products/greenpak-programmable-mixed-signal-products/greenpak-system-programmability/slg46826-greenpak-programmable-mixed-signal-matrix-system-programmabilityTable
| Field | Current value | Datasheet / official source value | Result |
|---|---|---|---|
| Manufacturer Part Number | SLG46826V | SLG46826V | Match |
| Manufacturer Name | Renesas | Renesas | Match |
| Part Type | Integrated Circuits | Programmable mixed-signal matrix IC / GreenPAK | Acceptable but broad/non-normalized |
| Package or Case Code | TO | 20-pin STQFN/TQFN, 2.0 mm x 3.0 mm x 0.55 mm, 0.4 mm pitch | Mismatch |
| Pin count | 20 terminals / 20 footprint pads | 20-pin STQFN for SLG46826V | Match |
| Datasheet URL | Renesas product page | Official datasheet document URL above | Official but not direct datasheet |
| Description | Programmable mixed-signal matrix IC with MTP NVM, dual supplies, GPIO, comparators, LUT/DFF/counter blocks, oscillators, I2C | Matches datasheet/product summary | Match |
Table
| Item | Datasheet value |
|---|---|
| Function | GreenPAK programmable mixed-signal matrix IC with in-system programmability |
| Memory | Multiple-time programmable NVM; includes 2-kbit I2C-compatible EEPROM emulation |
| Interface | I2C protocol interface on SCL/SDA |
| I/O resources | Product summary lists 17 GPIO/GPO resources; STQFN pinout exposes IO0–IO14 plus dedicated SCL/SDA pins |
| Analog comparators | 4 total: two high-speed rail-to-rail ACMPxH and two low-power rail-to-rail ACMPxL |
| VDD operating range | 2.3 V to 5.5 V; 2.5 V minimum during NVM write/erase |
| VDD2 operating range | 1.71 V to 5.5 V, with VDD2 <= VDD |
| Operating temperature | -40 °C to +85 °C |
| Required VDD capacitor | 0.1 µF minimum at VDD |
| Package for SLG46826V | STQFN 20L, 2 mm x 3 mm x 0.55 mm, 0.4 mm pitch |
| Ordering | SLG46826V = 20-pin STQFN; TR suffix is legacy |
Table
| Pin | Current terminal | Current pin type | Datasheet primary / alternate function | Result |
|---|---|---|---|---|
| 1 | VDD | Power In | Power Supply | Match |
| 2 | IO0 | Bi-Directional | GPIO; I2C_EXPAND_0; EXT_OSC0_IN | Match |
| 3 | IO1 | Bi-Directional | GPIO with OE; EXT_Vref analog comparator negative input | Match |
| 4 | IO2 | Bi-Directional | GPIO; EXT_SLA_0 | Match |
| 5 | IO3 | Bi-Directional | GPIO; EXT_SLA_1 | Match |
| 6 | IO4 | Bi-Directional | GPIO with OE; EXT_SLA_2 | Match |
| 7 | IO5 | Bi-Directional | GPIO with OE; EXT_SLA_3; I2C_EXPAND_1 | Match |
| 8 | SCL | Input | I2C serial clock input | Match |
| 9 | SDA | Bi-Directional | I2C serial data input/output | Match |
| 10 | IO6 | Output | GPO; I2C_EXPAND_2 | Match |
| 11 | GND | Ground | Ground | Match |
| 12 | IO7 | Output | GPO | Match |
| 13 | IO8 | Bi-Directional | GPIO with OE; EXT_OSC2_IN | Match |
| 14 | VDD2 | Power In | Power Supply 2; IO7–IO14 domain; VDD2 <= VDD | Match |
| 15 | IO9 | Bi-Directional | GPIO with OE; Vref1_OUT; I2C_EXPAND_3 | Match |
| 16 | IO10 | Bi-Directional | GPIO with OE; Vref0_OUT; EXT_OSC1_IN | Match |
| 17 | IO11 | Bi-Directional | GPIO with OE; ACMP3L+ analog comparator input | Match |
| 18 | IO12 | Bi-Directional | GPIO with OE; ACMP2L+ analog comparator input | Match |
| 19 | IO13 | Bi-Directional | GPIO with OE; ACMP1H+ analog comparator input | Match |
| 20 | IO14 | Bi-Directional | GPIO with OE; ACMP0H+ analog comparator input | Match |
Power, Ground, Communication, and Digital I/O. Each physical pin appears once only, and the assignments are compatible with the datasheet. Dedicated SCL/SDA are grouped as Communication; IO6/IO7 are grouped under Digital I/O with Output pin type, which is acceptable.SLG46826V.kicad_mod.Table
| Footprint item | Current footprint | Datasheet / land-pattern reference | Result |
|---|---|---|---|
| Pad count | 20 SMD perimeter pads | 20-pin STQFN | Match |
| Body / fab outline | 2.0 mm x 3.0 mm | STQFN 20L 2 mm x 3 mm | Match |
| Pitch | 0.4 mm | 0.4 mm | Match |
| Main pad size | mostly 0.210 mm x 0.465 mm | Land pattern extraction shows about 0.18 mm pad width and 0.45 mm length; package lead width tolerance is ±0.05 mm | Close / acceptable from extracted data |
| Corner/special pad sizes | 0.210 mm x 0.390 mm and one 0.210 mm x 0.565 mm pad | Land-pattern extraction includes 0.375 mm and 0.550 mm dimensions | Close / acceptable from extracted data |
| Overall land span | approximately 2.30 mm x 3.30 mm from pad extents | Datasheet land pattern extraction: 2.30 mm x 3.30 mm | Match |
| Pin 1 marker | Present near pad 1 | Required for orientation | Match |
| Exposed thermal pad | None present | No exposed pad identified in extracted STQFN package data | No mismatch found |
TOSTQFN 20L 2 mm x 3 mm x 0.55 mm, 0.4 mm pitch for SLG46826V20-TQFN if using Flux autocomplete, or a more specific editable value such as STQFN-20 2x3mm 0.4mm if allowed.Integrated CircuitsIntegrated Circuit; datasheet-specific classification is programmable mixed-signal IC / GreenPAK.Package or Case Code metadata from TO to the proper STQFN/TQFN package classification.Scope
Source Datasheet
Current Part Information in Flux
Key Datasheet Specs
Schematic Symbol / Terminal Cross-Check
Footprint Cross-Check
Mismatches / Issues Flagged
Review Outcome