Part Audit Review
Thought for 10 sec
I’ll rename the 16 affected terminals to the exact datasheet strings, then verify the corrected pin-number/name mapping.
Worked for 47 sec
Corrected all 16 pin-name typos to match the datasheet. Verified the updated names retain their original pin numbers and symbol positions.
Organize the symbol with Pin Group, Section, orientation, and Terminal Order metadata.
Thought for 11 sec
I’ll organize all 89 terminals into broad functional groups, keep Section equal to Pin Group, apply consistent side orientations, and assign deterministic terminal ordering while preserving pin numbers and names.
Worked for 4 mins 6 sec
Organized all 89 terminals into nine broad functional groups with matching Sections, consistent Left/Right orientations, and deterministic ordering. Power pins are Top/order 1, grounds Bottom/order 10; verification confirms complete metadata and unique pin numbers 1–89.
Add descriptions and review
Add pin descriptions
Set pin types
Final symbol audit
Review paste aperture
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RV1103G1 Part Audit
Scope
Reviewed available part metadata, datasheet linkage, 89-terminal schematic symbol, QFN footprint source, pin numbering/names, and available datasheet specifications.
Datasheet
- Existing
Datasheet URL:https://lcsc.com/datasheet/lcsc_datasheet_2404251628_Rockchip-RV1103G1_C5307358.pdf - The property was already populated, so it was not changed.
- This is an LCSC-hosted copy rather than a Rockchip-hosted official URL. Rockchip's official product page confirms the device and core features, but the public full PDF found on the web is primarily available through mirrors/distributors.
- Attached/indexed datasheet queried by Flux identifies itself as RV1103 Datasheet Rev 1.1 (Rockchip Electronics, 2022). A newer Rev 1.5 mirror was found, so the currently linked copy should be reviewed for revision currency.
Part metadata
Table
| Field | Current value | Audit |
|---|---|---|
| MPN | RV1103G1 | Matches ordering table |
| Manufacturer Name | Rockchip | Correct |
| Description | QFN-88(9x9) Microcontrollers (MCU/MPU/SOC) ROHS | Broadly correct; more accurately a vision processor SoC with integrated DDR2, NPU, ISP, codec, and Ethernet PHY |
| Package or Case Code | QFN | Correct but underspecified; datasheet calls out QFN88, 9 x 9 mm, 0.35 mm pitch |
| Terminal count | 89 | Correct representation: 88 perimeter pins plus exposed VSS pad |
| Part Type | Integrated Circuits | Acceptable but generic |
| Compliance | Rohs | Matches ordering information |
| Designator Prefix | IC | Acceptable |
| Library subtype | Logic | Misleading for this SoC |
| Library logic function | AND | Incorrect/misclassified; this is not an AND-gate logic IC |
| Library manufacturer facet | Other | Inconsistent with Manufacturer Name = Rockchip |
| Sourcing IDs | None | LCSC listing is C5307358, but no LCSC property is populated |
Key datasheet specifications
- Single-core 32-bit Arm Cortex-A7 with NEON/FPU, 32 KB I-cache, 32 KB D-cache, 128 KB L2 cache.
- Integrated MCU and 512 Mb DDR2 for RV1103G1.
- NPU up to 0.5 TOPS, supporting INT4/INT8/INT16.
- ISP up to 4 MP at 30 fps; dual 2-lane MIPI CSI D-PHY interfaces, combinable as four lanes; up to 1.5 Gbps/lane.
- H.265/H.264 encode up to 4 MP at 30 fps; JPEG up to 4 MP at 60 fps.
- Integrated 10/100 Ethernet MAC and PHY, USB 2.0 host/device, SDIO 3.0, FSPI, SPI, I2C, UART, audio codec, ADC, PWM and GPIO.
- Package: RoHS QFN88, 9 x 9 mm, 0.35 mm pitch, MSL3.
- Maximum junction temperature: 125 °C. Typical thermal resistance: θJA 32.1 °C/W, θJB 12.5 °C/W, θJC 9.3 °C/W.
- Absolute maxima include 0.99 V for DVDD/PMU 0.9 V groups, 1.98 V for 1.8 V groups, and 3.63 V for 3.3 V/GPIO groups. Datasheet leaves some CPU/DDR maxima as TBD in the queried revision.
Symbol and pin audit
- Pin numbers are complete and unique from 1 through 89.
- Exposed pad is represented as pin 89
VSS; datasheet labels itVSS E-PAD. This numbering convention is reasonable, although the package is marketed as QFN88. - The functional pin sequence agrees with the datasheet pin-number table, including Ethernet pins 67-72, power pins 73-75, MIPI/LVDS pins 76-88, and exposed VSS.
- All 89 terminals lack
Pin Description,Pin Group,Section, andTerminal Order. - All 89 terminals have
Pin Type = Unspecified; therefore ERC semantics are incomplete.
Confirmed pin-name text mismatches/typos
The pin numbers/functions are aligned, but these symbol names contain transcription errors relative to the datasheet naming:
Table
| Pin | Current symbol text | Datasheet text / correction |
|---|---|---|
| 4 | I2C4_SCL_M2/UART5_TX_M2/_GPIO3_C7_D | Remove leading underscore before GPIO3_C7_D |
| 5 | I2C4_SDA_M2/UART5_RX_M2/_GPIO3_D0_D | Remove leading underscore before GPIO3_D0_D |
| 11 | .../GP_IO3_A4_D | .../GPIO3_A4_D |
| 12 | PWM11_IR_M0_/GPIO3_A5_U | PWM11_IR_M0/GPIO3_A5_U |
| 13 | JTAG_HPMCU__TMS_M1 | JTAG_HPMCU_TMS_M1 |
| 14 | JTAG_HPMCU__TCK_M1 | JTAG_HPMCU_TCK_M1 |
| 49 | JTAG_HPMCU_TCK__M0 | JTAG_HPMCU_TCK_M0 |
| 50 | JTAG_HPMCU_TMS__M0 | JTAG_HPMCU_TMS_M0 |
| 54 | AUD_DSM__N | AUD_DSM_N |
| 55 | _AUD_DSM_P | AUD_DSM_P |
| 56 | GPIO1_D1__D | GPIO1_D1_D |
| 57 | GPIO1_D_0_D | GPIO1_D0_D |
| 60 | GPIO1_C5__D | GPIO1_C5_D |
| 61 | GPIO1_C4__D | GPIO1_C4_D |
| 62 | SPI0_MIS_O_M0 | SPI0_MISO_M0 |
| 63 | SPI0_MOSI__M0 | SPI0_MOSI_M0 |
Letter-case suffixes (
_U/_D/_Z versus datasheet _u/_d/_z) are normalization differences, not functional mismatches.Footprint audit
Footprint source:
QFN35P900X900X95-89N-D.kicad_mod.- 88 perimeter pads plus one exposed pad: matches the package pin structure.
- Body fab outline: 9.0 x 9.0 mm: matches datasheet.
- Pitch: 0.35 mm: matches datasheet.
- Perimeter copper pads: 0.15 x 0.85 mm.
- Exposed pad: 6.6 x 6.6 mm.
- Courtyard: 10.25 x 10.25 mm.
- Pin-1 identification exists as a fab chamfer and silkscreen circle.
- Pad numbering/orientation proceeds consistently around all four sides.
Footprint concerns
- The text-extracted datasheet package drawing did not expose exact lead-width, lead-length, and exposed-pad dimensions, so the 0.15 x 0.85 mm lands and 6.6 x 6.6 mm center land could not be conclusively dimension-checked against the manufacturer's detailed drawing.
- The entire 6.6 x 6.6 mm exposed pad uses one full-size paste aperture. For a large QFN thermal pad, segmented/windowed paste is normally preferred to control solder volume, voiding, and package float. This is a manufacturability concern even if the copper land dimension is correct.
- No thermal-via pattern is part of the footprint. Thermal vias are board/application dependent, but should be designed in the PCB when heat dissipation and ground impedance require them.
- Package height
0.95 mmis encoded in the footprint name but was not verified from the OCR-extracted package dimension table.
Overall result
Not fully datasheet-complete. Core identity, package family, pin count, numbering, and functional pin assignment are substantially correct. The main issues are numerous pin-name transcription typos, absent pin descriptions/types/grouping metadata, misleading library classification (
Logic / AND), a non-manufacturer-hosted and potentially outdated datasheet link, and an exposed-pad paste aperture that should be reviewed before manufacturing.Scope
Datasheet
Part metadata
Key datasheet specifications
Symbol and pin audit
Confirmed pin-name text mismatches/typos
Footprint audit
Footprint concerns
Overall result
